Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 123
SAM9G20
18.5.2 Bus Matrix Slave Configuration Registers
Name:MATRIX_SCFG0...MATRIX_SCFG4
Access:Read/Write
SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking very slow slaves when very long bursts are used.
This limit should not be very small though. Unreasonably small values break every burst and the Bus Matrix arbitrates without performing
any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE.
DEFMSTR_TYPE: Default Master Type
0: No Default Master
At the end of current slave access, if no other master request is pending, the slave is disconnected from all masters.
This results in one cycle latency for the first access of a burst transfer or for a single access.
1: Last Default Master
At the end of current slave access, if no other master request is pending, the slave stays connected with the last master having accessed it.
This results in not having the one cycle latency when the last master tries to access the slave again.
2: Fixed Default Master
At the end of the current slave access, if no other master request is pending, the slave connects to the fixed master whose
number has been written in the FIXED_DEFMSTR field.
This results in not having the one cycle latency when the fixed master tries to access the slave again.
FIXED_DEFMSTR: Fixed Default Master
This is the number of the Default Master for this slave. Only used if DEFMASTR_TYPE is 2. Specifying the number of a master which is
not connected to the selected slave is equivalent to setting DEFMASTR_TYPE to 0.
ARBT: Arbitration Type
0: Round-Robin Arbitration
1: Fixed Priority Arbitration
2: Reserved
3: Reserved
31 30 29 28 27 26 25 24
–––––– ARBT
23 22 21 20 19 18 17 16
– FIXED_DEFMSTR DEFMSTR_TYPE
15 14 13 12 11 10 9 8
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76543210
SLOT_CYCLE