Datasheet

 2017 Microchip Technology Inc. DS60001516A-page 119
SAM9G20
18.4.1 Arbitration Rules
Each arbiter has the ability to arbitrate between two or more different master’s requests. In order to avoid burst breaking and also to provide
the maximum throughput for slave interfaces, arbitration may only take place during the following cycles:
1. Idle Cycles: when a slave is not connected to any master or is connected to a master which is not currently accessing it.
2. Single Cycles: when a slave is currently doing a single access.
3. End of Burst Cycles: when the current cycle is the last cycle of a burst transfer. For defined length burst, predicted end of burst
matches the size of the transfer but is managed differently for undefined length burst (see Section 18.4.1.1 “Undefined Length Burst
Arbitration”).
4. Slot Cycle Limit: when the slot cycle counter has reached the limit value indicating that the current master access is too long and
must be broken (see Section 18.4.1.2 “Slot Cycle Limit Arbitration”).
18.4.1.1 Undefined Length Burst Arbitration
In order to avoid too long slave handling during undefined length bursts (INCR), the Bus Matrix provides specific logic in order to re-arbi-
trate before the end of the INCR transfer.
A predicted end of burst is used as for defined length burst transfer, which is selected between the following:
1. Infinite: no predicted end of burst is generated and therefore INCR burst transfer is never broken.
2. Four beat bursts: predicted end of burst is generated at the end of each four beat boundary inside INCR transfer.
3. Eight beat bursts: predicted end of burst is generated at the end of each eight beat boundary inside INCR transfer.
4. Sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat boundary inside INCR transfer.
This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG).
18.4.1.2 Slot Cycle Limit Arbitration
The Bus Matrix contains specific logic to break too long accesses such as very long bursts on a very slow slave (e.g., an external low
speed memory). At the beginning of the burst access, a counter is loaded with the value previously written in the SLOT_CYCLE field of
the related Slave Configuration Register (MATRIX_SCFG) and decreased at each clock cycle. When the counter reaches zero, the arbiter
has the ability to re-arbitrate at the end of the current byte, half word or word transfer.
18.4.2 Round-Robin Arbitration
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave in a round-robin manner.
If two or more master’s requests arise at the same time, the master with the lowest number is first serviced then the others are serviced
in a round-robin manner.
There are three round-robin algorithms implemented:
• Round-Robin arbitration without default master
• Round-Robin arbitration with last access master
• Round-Robin arbitration with fixed default master
18.4.2.1 Round-Robin Arbitration without Default Master
This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch requests from different masters to the same
slave in a pure round-robin manner. At the end of the current access, if no other request is pending, the slave is disconnected from all
masters. This configuration incurs one latency cycle for the first access of a burst. Arbitration without default master can be used for mas-
ters that perform significant bursts.
18.4.2.2 Round-Robin Arbitration with Last Access Master
This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove the one latency cycle for the last
master that accessed the slave. At the end of the current transfer, if no other master request is pending, the slave remains connected to
the last master that performs the access. Other non privileged masters still get one latency cycle if they want to access the same slave.
This technique can be used for masters that mainly perform single accesses.
18.4.2.3 Round-Robin Arbitration with Fixed Default Master
This is another biased round-robin algorithm, it allows the Bus Matrix arbiters to remove the one latency cycle for the fixed default master
per slave. At the end of the current access, the slave remains connected to its fixed default master. Requests attempted by this fixed default
master do not cause any latency whereas other non privileged masters get one latency cycle. This technique can be used for masters that
mainly perform single accesses.