Datasheet

SAM9G20
DS60001516A-page 118  2017 Microchip Technology Inc.
18. SAM9G20 Bus Matrix
18.1 Overview
The Bus Matrix implements a multi-layer AHB based on the AHB-Lite protocol that enables parallel access paths between multiple AHB
masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects 6 AHB Masters to 5 AHB Slaves.
The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected
directly (zero cycle latency).
The Bus Matrix user interface is compliant with the Arm Advanced High-performance Bus and provides a Chip Configuration User Inter-
face with registers that allow the Bus Matrix to support application specific features.
18.2 Memory Mapping
The Bus Matrix provides one decoder for every AHB Master Interface. The decoder offers each AHB Master several memory mappings.
In fact, depending on the product, each memory area may be assigned to several slaves. Booting at the same address while using different
AHB slaves (i.e., external RAM, internal ROM or internal Flash, etc.) becomes possible.
The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that performs remap action for every master
independently.
18.3 Special Bus Granting Techniques
The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from some masters. This mech-
anism reduces latency at first accesses of a burst or single transfer. The bus granting mechanism sets a default master for every slave.
At the end of the current access, if no other request is pending, the slave remains connected to its associated default master. A slave can
be associated with three kinds of default masters: no default master, last access master and fixed default master.
18.3.1 No Default Master
At the end of the current access, if no other request is pending, the slave is disconnected from all masters. No Default Master suits Low
Power mode.
18.3.2 Last Access Master
At the end of the current access, if no other request is pending, the slave remains connected to the last master that performed an access
request.
18.3.3 Fixed Default Master
At the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike last access master,
the fixed master doesn’t change unless the user modifies it by a software action (field FIXED_DEFMSTR of the related MATRIX_SCFG).
To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration Registers, one for
each slave, that set a default master for each slave. The Slave Configuration Register contains two fields, DEFMSTR_TYPE and
FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field is used to select the default master type (no default, last access master, fixed default
master) whereas the 4-bit FIXED_DEFMSTR field is used to select a fixed default master provided that DEFMSTR_TYPE is set to fixed
default master. Refer to Section 18.5 “Bus Matrix (MATRIX) User Interface”.
18.4 Arbitration
The Bus Matrix provides an arbitration mechanism that reduces latency when conflicting cases occur, in particular when two or more mas-
ters try to access the same slave at the same time. One arbiter per AHB slave is provided, thus arbitrating each slave differently.
The Bus Matrix provides the user the possibility to choose between 2 arbitration types for each slave:
1. Round-Robin Arbitration (the default)
2. Fixed Priority Arbitration
This choice is made through the field ARBT of the Slave Configuration Registers (MATRIX_SCFG).
Each algorithm may be complemented by selecting a default master configuration for each slave.
When a re-arbitration has to be done, it is realized only under specific conditions described in Section 18.4.1 “Arbitration Rules”.