32-BIT ARM-BASED MICROPROCESSORS SAM9G20 Description The SAM9G20 embedded microprocessor unit is based on the integration of an Arm926EJ-S™ processor with fast ROM and RAM memories and a wide range of peripherals. The SAM9G20 embeds an Ethernet MAC, one USB Device Port, and a dual port USB Host controller with on-chip USB transceivers. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface.
SAM9G20 - Periodic Interval Timer, Watchdog Timer and Real-time Timer • Reset Controller (RSTC) - Based on a Power-on Reset Cell, Reset Source Identification and Reset Output Control • Clock Generator (CKGR) - Selectable 32768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power Supply, Providing a Permanent Slow Clock - 3 to 20 MHz On-chip Oscillator, One up to 800 MHz PLL and One up to 100 MHz PLL • Power Management Controller (PMC) - Very Slow Clock Operating Mode, Software
SAM9G20 - Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode • IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins • Required Power Supplies - 0.9V to 1.1V for VDDBU, VDDCORE, VDDPLL - 1.65 to 3.6V for VDDOSC - 1.65V to 3.6V for VDDIOP (Peripheral I/Os) - 3.0V to 3.6V for VDDUSB - 3.0V to 3.6V VDDANA (Analog-to-Digital Converter) - Programmable 1.65V to 1.95V or 3.0V to 3.
Block Diagram FIQ IRQ0–IRQ2 AIC DRXD DTXD PCK0–PCK1 DBGU In-Circuit Emulator Filter Filter M CK IS PC I_ K IS D0 I_ –I V IS SY SI_ I_ N D7 HS C YN C HD P HD A M A HD PB HD M B I_ I_ 10/100 Ethernet MAC Arm926EJ-S Processor ICache 32 Kbytes DCache 32 Kbytes MMU FIFO I PMC Image Sensor Interface USB OHCI DMA DMA D PLLB Main Oscillator WDT PIT RC Osc.
SAM9G20 2. Signal Description Table 2-1: Signal Description List Signal Name Function Type Active Level Comments Power Supplies VDDIOM EBI I/O Lines Power Supply Power – 1.65–1.95 V or 3.0–3.6 V VDDIOP Peripherals I/O Lines Power Supply Power – 1.65–3.6 V VDDBU Backup I/O Lines Power Supply Power – 0.9–1.1 V VDDANA Analog Power Supply Power – 3.0–3.6 V VDDPLL PLL Power Supply Power – 0.9–1.1 V VDDOSC Oscillator Power Supply Power – 1.65–3.
SAM9G20 Table 2-1: Signal Description List Signal Name Function Type Active Level I/O Low Input – Comments Reset/Test NRST Microprocessor Reset TST Test Mode Select Pull-up resistor Pull-down resistor. Accepts between 0V and VDDBU.
SAM9G20 Table 2-1: Signal Description List Signal Name Function Type Active Level Comments NAND Flash Support NANDCS NAND Flash Chip Select Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low NANDALE NAND Flash Address Latch Enable Output Low NANDCLE NAND Flash Command Latch Enable Output Low SDRAM Controller - SDRAMC SDCK SDRAM Clock Output – SDCKE SDRAM Clock Enable Output High SDCS SDRAM Controller Chip Select Output Low B
SAM9G20 Table 2-1: Signal Description List Signal Name Function RF SSC Receive Frame Sync Type Active Level I/O – Comments Timer/Counter - TCx TCLKx TC Channel x External Clock Input Input – TIOAx TC Channel x I/O Line A I/O – TIOBx TC Channel x I/O Line B I/O – Serial Peripheral Interface - SPIx SPIx_MISO Master In Slave Out I/O – SPIx_MOSI Master Out Slave In I/O – SPIx_SPCK SPI Serial Clock I/O – SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low SPIx_NPCS1–SPIx_NPCS3
SAM9G20 Table 2-1: Signal Description List Signal Name Function Type Active Level Comments Image Sensor Interface - ISI ISI_D0-ISI_D11 Image Sensor Data Input – ISI_MCK Image Sensor Reference Clock Output – ISI_HSYNC Image Sensor Horizontal Synchro Input – ISI_VSYNC Image Sensor Vertical Synchro Input – ISI_PCK Image Sensor Data clock Input – Analog-to-Digital Converter - ADC AD0-AD3 Analog Inputs Analog – ADVREF Analog Positive Reference Analog – ADTRG ADC Trigger Input
SAM9G20 3. Package and Pinout The SAM9G20 is available in the following Green-compliant packages: • 217-ball LFBGA, 15 x 15 mm x 1.4 mm (0.8 mm pitch) • 247-ball TFBGA, 10 x 10 x 1.1 mm (0.5 mm pitch) 3.1 217-ball LFBGA Package Outline Figure 3-1 shows the orientation of the 217-ball LFBGA package. A detailed mechanical description is given in Section 41.1 “217-ball LFBGA Package Drawing”.
SAM9G20 Table 3-1: Pinout for 217-ball LFBGA Package (Continued) Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name A15 PC5 E2 D5 K17 PB15 R14 PA21 A16 PC6 E3 D3 L1 GND R15 PA23 A17 PC4 E4 D4 L2 PC26 R16 PA24 B1 SDCK E14 HDPA L3 PC25 R17 PA29 B2 CFIOR/NBS1/NWR1 E15 HDMA L4 VDDOSC T1 NC B3 SDCS/NCS1 E16 GNDBU L14 PA28 T2 GNDPLL B4 SDA10 E17 XOUT32 L15 PB9 T3 PC0 B5 A3 F1 D13 L16 PB8 T4 PC1 B6 A7 F2 SDWE L17 PB14 T5
SAM9G20 Table 3-1: Pinout for 217-ball LFBGA Package (Continued) Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name C17 SHDN J3 VDDIOM P12 PA3 U16 PA18 D1 D9 J4 PC16 P13 PA7 U17 VDDIOP D2 D2 J8 GND P14 PA9 D3 RAS J9 GND P15 PA26 D4 D0 J10 GND P16 PA25 3.3 247-ball TFBGA Package Outline Figure 3-2 shows the orientation of the 247-ball TFBGA package. A detailed mechanical description is given in Section 41.2 “247-ball TFBGA Package Drawing”.
SAM9G20 Table 3-2: Pinout for 247-ball TFBGA Package (Continued) Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name B4 D9 F17 PC9 L5 ADVREF R11 PA19 B5 D7 F18 PC12 L6 PC2 R12 PA26 B6 D3 G2 PC26 L7 GND R13 PB1 B7 D2 G3 PC25 L8 GND R14 GND B8 RAS G5 PC24 L9 GND R15 PB7 B9 CAS G6 PC21 L10 GND R17 PB14 B10 NWR2/NBS2/A1 G8 VDDCORE L11 VDDCORE R18 PB9 B11 A3 G9 A5 L12 GND T2 PA1 B13 A10 G10 VDDCORE L13 OSCSEL T3 PB10 B1
SAM9G20 Table 3-2: Pinout for 247-ball TFBGA Package (Continued) Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name E7 D0 J9 VDDIOM N15 VDDIOP V9 PA14 E8 CFIOW/NBS3/NWR3 J10 VDDIOM N17 TDO V10 VDDIOP E9 GND J11 VDDIOM N18 TDI V11 PA20 E10 A4 J12 GND P2 PB24 V12 PA22 E11 A8 J13 GND P3 PB22 V13 VDDIOP E12 VDDIOM J14 WKUP P5 GND V14 PA30 E13 BA0/A16 J15 DDP P6 GND V15 PB0 E14 PC8 J17 DDM P7 PA6 V16 GND E15 PC4 J18 VDDIOP
SAM9G20 4. Power Considerations 4.1 Power Supplies The SAM9G20 has several types of power supply pins. Some supply pins share common ground (GND) pins whereas others have separate grounds. See Table 4-1. Table 4-1: SAM9G20 Power Supply Pins Pin(s) Item(s) powered Range Nominal VDDCORE Core, including the processor Embedded memories Peripherals 0.9–1.1 V 1.0V 1.65–1.95 V 1.8V VDDIOM External Bus Interface I/O lines 3.0–3.6 V 3.3V 1.65–3.6 V – 1.65–1.95 V 1.8V 3.0–3.6 V 3.
SAM9G20 Figure 4-1: VDDCORE and VDDIO Constraints at Startup VDD (V) VDDIO VDDIOtyp VDDIO > VOH VOH(2.6V) VDDCORE VDDCOREtyp 0.7V VT+ (0.5V) t <--------------------- t1----------------------> < t2 >< t3 ><------------- t4 ------------> Core Supply POR output SLCK VDDCORE and VDDBU are controlled by Power-on-Reset (POR) to guarantee that these power sources reach their target values prior to the release of POR. (See Figure 4-1.
SAM9G20 Figure 4-2: Power-up Sequence Implementation Example on AT91SAM9G20-EK Rev.C 10 SQUARE CM COPPER AREA FOR HEAT SINKING WITH NO SOLDER MASK R168 MN1 LT1963AEQ-3.
SAM9G20 5. I/O Line Considerations 5.1 JTAG Port Pins TMS, TDI and TCK are schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven at up to VDDIOP, and have no pull-up resistor. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations. The NTRST signal is described in Section 5.3 “Reset Pins”.
SAM9G20 6. Processor and Architecture 6.
SAM9G20 6.2.1 Matrix Masters The Bus Matrix of the SAM9G20 manages six Masters, which means that each master can perform an access concurrently with others, according the slave it accesses is available. Each Master has its own decoder that can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings.
SAM9G20 6.3 • • • • Peripheral DMA Controller Acting as one Matrix Master Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor. Next Pointer Support, forbids strong real-time constraints on buffer management.
SAM9G20 7.
SAM9G20 A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High Performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. Banks 1 to 7 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS7.
SAM9G20 • Automatic detection of valid application • Bootloader on a non-volatile memory - SDCard (boot ROM does not support high capacity SDCards.) - NAND Flash - SPI DataFlash and Serial Flash connected on NPCS0 and NPCS1 of the SPI0 - EEPROM on TWI • SAM-BA® Boot in case no valid program is detected in external NVM, supporting - Serial communication on a DBGU - USB Device HS Port 7.1.1.
SAM9G20 • Multiple Wait State Management - Programmable Wait State Generation - External Wait Request - Programmable Data Float Time • Slow Clock mode supported 7.2.
SAM9G20 8. System Controller The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface embeds also the registers allowing to configure the Matrix and a set of registers for the chip configuration.
SAM9G20 8.1 System Controller Block Diagram Figure 8-1: SAM9G20 System Controller Block Diagram System Controller VDDCORE Powered nirq nfiq irq0–irq2 fiq periph_irq[2..
SAM9G20 8.2 Reset Controller • Based on two Power-on-Reset cells - one on VDDBU and one on VDDCORE • Status of the last reset - Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or watchdog reset • Controls the internal resets and the NRST pin output - Allows shaping a reset signal for the external devices 8.
SAM9G20 8.5 Power Management Controller • Provides: - the Processor Clock PCK - the Master Clock MCK, in particular to the Matrix and the memory interfaces.
SAM9G20 8.8 Real-time Timer • Real-time Timer 32-bit free-running back-up Counter • Integrates a 16-bit programmable prescaler running on slow clock • Alarm Register capable of generating a wake-up of the system through the Shutdown Controller 8.9 General-purpose Backup Registers • Four 32-bit general-purpose backup registers 8.
SAM9G20 9. Peripherals 9.1 User Interface The peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each User Peripheral is allocated 16 Kbytes of address space. A complete memory map is presented in Figure 7-1. 9.2 Peripheral Identifiers Table 9-1 defines the Peripheral Identifiers of the SAM9G20.
SAM9G20 Table 9-1: Peripheral Identifiers (Continued) Peripheral ID Peripheral Mnemonic Peripheral Name External Interrupt 29 AIC Advanced Interrupt Controller IRQ0 30 AIC Advanced Interrupt Controller IRQ1 31 AIC Advanced Interrupt Controller IRQ2 Note: 9.2.1 9.2.1.1 Setting AIC, SYSC, UHP, ADC and IRQ0-2 bits in the clock set/clear registers of the PMC has no effect. The ADC clock is automatically started for the first conversion.
SAM9G20 9.3.
SAM9G20 9.3.
SAM9G20 9.3.
SAM9G20 9.4 9.4.
SAM9G20 The USART1 and USART2 do not implement all the modem signals. Only RTS and CTS (RTS1 and CTS1, RTS2 and CTS2, respectively) are implemented in these USARTs for other features. Thus, programming the USART1, USART2 or the USART3 in Modem Mode may lead to unpredictable results. In these USARTs, the commands relating to the Modem Mode have no effect and the status bits relating the status of the modem signals are never activated. 9.4.
SAM9G20 9.4.8 USB Device Port • • • • • • USB V2.0 full-speed compliant, 12 MBits per second Embedded USB V2.0 full-speed transceiver Embedded 2,432-byte dual-port RAM for endpoints Suspend/Resume logic Ping-pong mode (two memory banks) for isochronous and bulk endpoints Six general-purpose endpoints - Endpoint 0 and 3: 64 bytes, no ping-pong mode - Endpoint 1 and 2: 64 bytes, ping-pong mode - Endpoint 4 and 5: 512 bytes, ping-pong mode • Embedded pad pull-up 9.4.
SAM9G20 10. Arm926EJ-S Processor Overview 10.1 Overview The Arm926EJ-S processor is a member of the Arm9™ family of general-purpose microprocessors. The Arm926EJ-S implements Arm architecture version 5TEJ and is targeted at multi-tasking applications where full memory management, high performance, low die size and low power are all important features.
SAM9G20 10.
SAM9G20 10.3 10.3.1 Arm9EJ-S Processor Arm9EJ-S Operating States The Arm9EJ-S processor can operate in three different states, each with a specific instruction set: • Arm state: 32-bit, word-aligned Arm instructions. • THUMB state: 16-bit, halfword-aligned Thumb instructions. • Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 10.3.
SAM9G20 Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources. 10.3.7 Arm9EJ-S Registers The Arm9EJ-S core has a total of 37 registers: • 31 general-purpose 32-bit registers • Six 32-bit status registers Table 10-1 shows all the registers in all modes.
SAM9G20 In all modes and due to a software agreement, register r13 is used as stack pointer. The use and the function of all the registers described above should obey Arm Procedure Call Standard (APCS) which defines: • constraints on the use of registers • stack conventions • argument passing and result return For more details, refer to Arm Software Development Kit. The Thumb state register set is a subset of the Arm state set.
SAM9G20 More than one exception can happen at a time, therefore the Arm9EJ-S takes the arisen exceptions according to the following priority order: • • • • • • Reset (highest priority) Data Abort FIQ IRQ Prefetch Abort BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority) The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive.
SAM9G20 Table 10-2 gives the Arm instruction mnemonic list.
SAM9G20 10.3.
SAM9G20 Table 10-4: Thumb Instruction Mnemonic List (Continued) Mnemonic Operation Mnemonic Operation LDR Load Word STR Store Word LDRH Load Half Word STRH Store Half Word LDRB Load Byte STRB Store Byte LDRSH Load Signed Halfword LDRSB Load Signed Byte LDMIA Load Multiple STMIA Store Multiple PUSH Push Register to stack POP Pop Register from stack Conditional Branch BKPT Breakpoint BCC 10.
SAM9G20 Table 10-5: CP15 Registers (Continued) Register Name Read/Write (1) 13 Context ID Read/Write 14 Reserved None 15 Test configuration Read/Write Note 1: Register locations 0,5, and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field. 2: Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field. 10.4.
SAM9G20 10.5 Memory Management Unit (MMU) The Arm926EJ-S processor implements an enhanced Arm architecture v5 MMU to provide virtual memory features required by operating systems like Symbian OS®, Windows CE, and Linux. These virtual memory features are memory access permission controls and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13.
SAM9G20 There are three sizes of page-mapped accesses and one size of section-mapped access. Page-mapped accesses are for large pages, small pages and tiny pages. The translation process always begins with a level one fetch. A section-mapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. For further details on the MMU, refer to chapter 3 in Arm926EJ-S Technical Reference Manual. 10.5.
SAM9G20 Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used to decide whether all, half or none is written back to memory. DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page 4-5 in Arm926EJS TRM).
SAM9G20 The following table gives an overview of the supported transfers and different kinds of transactions they are used for.
SAM9G20 11. Debug and Test 11.1 Overview The SAM9G20 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel.
SAM9G20 11.2 Block Diagram Figure 11-1: Debug and Test Block Diagram TMS TCK TDI NTRST ICE/JTAG TAP Boundary Port JTAGSEL TDO RTCK POR Reset and Test Arm9EJ-S TST ICE-RT PDC DBGU PIO Arm926EJ-S DTXD DRXD TAP: Test Access Port DS60001516A-page 54 2017 Microchip Technology Inc.
SAM9G20 11.3 11.3.1 Application Examples Debug Environment Figure 11-2 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface.
SAM9G20 11.
SAM9G20 NTRST (optional in IEEE Standard 1149.1) is a Test-Reset input which is mandatory in Arm cores and used to reset the debug logic. On Microchip Arm926EJ-S-based cores, NTRST is a Power On Reset output. It is asserted on power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2.5 MCK periods. TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment controlling the test and not by the tested device.
SAM9G20 Table 11-2: SAM9G20 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type A14 IN/OUT 295 CONTROL 294 INPUT/OUTPUT 293 CONTROL A15 IN/OUT 292 INPUT/OUTPUT 291 CONTROL A16 IN/OUT 290 INPUT/OUTPUT 289 CONTROL A17 IN/OUT 288 INPUT/OUTPUT 287 CONTROL A18 IN/OUT 286 INPUT/OUTPUT 285 CONTROL A19 IN/OUT 284 INPUT/OUTPUT 283 CONTROL A2 IN/OUT 282 INPUT/OUTPUT 281 CONTROL A20 IN/OUT 280 INPUT/OUTPUT 279 CONTROL A21 IN/OUT 278 INPUT/OUTPUT 277
SAM9G20 Table 11-2: SAM9G20 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type CAS IN/OUT 260 CONTROL 259 INPUT/OUTPUT 258 CONTROL D0 IN/OUT 257 INPUT/OUTPUT 256 CONTROL D1 IN/OUT 255 INPUT/OUTPUT 254 CONTROL D10 IN/OUT 253 INPUT/OUTPUT 252 CONTROL D11 IN/OUT 251 INPUT/OUTPUT 250 CONTROL D12 IN/OUT 249 INPUT/OUTPUT 248 CONTROL D13 IN/OUT 247 INPUT/OUTPUT 246 CONTROL D14 IN/OUT 245 INPUT/OUTPUT 244 CONTROL D15 IN/OUT 243 INPUT/OUTPUT 242 C
SAM9G20 Table 11-2: SAM9G20 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type NANDWE IN/OUT 224 CONTROL 223 INPUT/OUTPUT 222 CONTROL NCS0 IN/OUT 221 INPUT/OUTPUT 220 CONTROL NCS1 IN/OUT 219 INPUT/OUTPUT 218 CONTROL NRD IN/OUT 217 INPUT/OUTPUT 216 CONTROL NRST IN/OUT 215 INPUT/OUTPUT 214 CONTROL NWR0 IN/OUT 213 INPUT/OUTPUT 212 CONTROL NWR1 IN/OUT 211 INPUT/OUTPUT 210 CONTROL NWR3 IN/OUT 209 208 INPUT/OUTPUT OSCSEL INPUT PA0 IN/OUT 207 INPU
SAM9G20 Table 11-2: SAM9G20 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type PA17 IN/OUT 189 Associated BSR Cells CONTROL 188 INPUT/OUTPUT 187 CONTROL PA18 IN/OUT 186 INPUT/OUTPUT 185 CONTROL PA19 IN/OUT 184 INPUT/OUTPUT 183 CONTROL PA2 IN/OUT 182 INPUT/OUTPUT 181 CONTROL PA20 IN/OUT 180 INPUT/OUTPUT 179 CONTROL PA21 IN/OUT 178 INPUT/OUTPUT 177 CONTROL PA22 IN/OUT 176 INPUT/OUTPUT 175 CONTROL PA23 IN/OUT 174 INPUT/OUTPUT 173 CONTROL PA24 IN
SAM9G20 Table 11-2: SAM9G20 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type PA5 IN/OUT 153 Associated BSR Cells CONTROL 152 INPUT/OUTPUT 151 CONTROL PA6 IN/OUT 150 INPUT/OUTPUT 149 CONTROL PA7 IN/OUT 148 INPUT/OUTPUT 147 CONTROL PA8 IN/OUT 146 INPUT/OUTPUT 145 CONTROL PA9 IN/OUT 144 INPUT/OUTPUT 143 CONTROL PB0 IN/OUT 142 INPUT/OUTPUT 141 CONTROL PB1 IN/OUT 140 INPUT/OUTPUT 139 CONTROL PB10 IN/OUT 138 INPUT/OUTPUT 137 CONTROL PB11 IN/OUT
SAM9G20 Table 11-2: SAM9G20 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type PB20 IN/OUT 117 CONTROL 116 INPUT/OUTPUT 115 CONTROL PB21 IN/OUT 114 INPUT/OUTPUT 113 CONTROL PB22 IN/OUT 112 INPUT/OUTPUT 111 CONTROL PB23 IN/OUT 110 INPUT/OUTPUT 109 CONTROL PB24 IN/OUT 108 INPUT/OUTPUT 107 CONTROL PB25 IN/OUT 106 INPUT/OUTPUT 105 CONTROL PB26 IN/OUT 104 INPUT/OUTPUT 103 CONTROL PB27 IN/OUT 102 INPUT/OUTPUT 101 CONTROL PB28 IN/OUT 100 INPUT/OUT
SAM9G20 Table 11-2: SAM9G20 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type PB9 IN/OUT 81 Associated BSR Cells CONTROL 80 INPUT/OUTPUT 79 CONTROL PC0 IN/OUT 78 INPUT/OUTPUT 77 CONTROL PC1 IN/OUT 76 INPUT/OUTPUT 75 CONTROL PC10 IN/OUT 74 INPUT/OUTPUT 73 CONTROL PC11 IN/OUT 72 INPUT/OUTPUT 71 – internal – 70 – internal – PC13 IN/OUT 69 CONTROL 68 INPUT/OUTPUT 67 CONTROL PC14 IN/OUT 66 INPUT/OUTPUT 65 CONTROL PC15 IN/OUT 64 INPUT/OUTPUT
SAM9G20 Table 11-2: SAM9G20 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type PC24 IN/OUT 45 Associated BSR Cells CONTROL 44 INPUT/OUTPUT 43 CONTROL PC25 IN/OUT 42 INPUT/OUTPUT 41 CONTROL PC26 IN/OUT 40 INPUT/OUTPUT 39 CONTROL PC27 IN/OUT 38 INPUT/OUTPUT 37 CONTROL PC28 IN/OUT 36 INPUT/OUTPUT 35 CONTROL PC29 IN/OUT 34 INPUT/OUTPUT 33 – internal – 32 – internal – PC30 IN/OUT 31 CONTROL 30 INPUT/OUTPUT 29 CONTROL PC31 IN/OUT 28 INPUT/OUT
SAM9G20 Table 11-2: SAM9G20 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type SDCK IN/OUT 09 Associated BSR Cells CONTROL 08 INPUT/OUTPUT 07 CONTROL SDCKE IN/OUT 06 INPUT/OUTPUT 05 CONTROL SDWE IN/OUT 04 INPUT/OUTPUT 03 CONTROL SHDN OUT 02 OUTPUT 01 TST INPUT INPUT 00 WKUP INPUT INPUT DS60001516A-page 66 2017 Microchip Technology Inc.
SAM9G20 11.5.6 JID Code Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 10 9 8 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 MANUFACTURER IDENTITY 5 4 MANUFACTURER IDENTITY 3 2 1 0 1 VERSION[31:28]: Product Version Number Set to 0x0. PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B24 MANUFACTURER IDENTITY[11:1] Set to 0x01F. Bit[0] required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B2_403F.
SAM9G20 12. Boot Program 12.1 Overview The Boot Program integrates different programs that manage download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB High Speed Device Port. The Boot program tries to detect SPI flash memories. The Serial Flash Boot program and DataFlash Boot program are executed. It looks for a sequence of seven valid Arm exception vectors in a Serial Flash or DataFlash connected to the SPI.
SAM9G20 Figure 12-1: Boot Program Algorithm Flow Diagram Device Setup SPI Serialflash Boot NPCS0 No Yes Download from Serial flash NPCS1 Run Yes Download from Dataflash NPCS1 Run Yes Download from NandFlash Run NandFlash Boot Yes Download from SDCARD Run SD Card Boot Yes Download from EEPROM Run TWI/EEPROM Boot DataFlash Boot NPCS0 DataFlash Boot NPCS1 Timeout 50ms.
SAM9G20 12.3 Device Initialization Initialization follows the steps described below: 1. 2. 3. 4. Stack setup for Arm supervisor mode Main Oscillator Frequency Detection C variable initialization PLL setup: PLLB is initialized to generate a 48 MHz clock necessary to use the USB Device. A register located in the Power Management Controller (PMC) determines the frequency of the main oscillator and thus the correct factor for the PLLB.
SAM9G20 Table 12-4: Input Frequencies Supported (OSCEL = 1) 11.05920 12.0 12.288 13.56 14.31818 14.7456 16.0 17.734470 18.432 20.0 24.0 24.576 25.0 28.224 32.0 33.0 40.0 48.0 50 Note: 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. Booting either on USB or on DBGU is possible with any of these input frequencies. Initialization of the DBGU serial port (115200 bauds, 8, N, 1) Jump to Serial Flash Boot sequence through NPCS0. If Serial Flash Boot succeeds, perform a remap and jump to 0x0.
SAM9G20 Figure 12-4: B Opcode 31 1 28 27 1 1 0 1 24 23 0 1 0 0 Offset (24 bits) Unconditional instruction: 0xE for bits 31 to 28 Load PC with PC relative addressing instruction: - Rn = Rd = PC = 0xF I==0 P==1 U offset added (U==1) or subtracted (U==0) W==1 12.4.2 Structure of Arm Vector 6 The Arm exception vector 6 is used to store information needed by the DataFlash boot program. This information is described below.
SAM9G20 Figure 12-6: Serial Flash Download Start Send status command (0x05) Is status OK ? No Jump to next boot solution Yes Read the first 8 instructions (0x0b). Decode the sixth Arm vector 8 vectors (except vector 6) are LDR or Branch instruction No Yes Read the SerialFlash into the internal SRAM. (code size to read in vector 6) Restore the reset value for the peripherals. Set the PC to 0 and perform the REMAP to jump to the downloaded application End 12.
SAM9G20 Figure 12-7: Serial DataFlash Download Start Send status command Is status OK ? No Jump to next boot solution Yes Read the first 8 instructions (32 bytes). Decode the sixth Arm vector 8 vectors (except vector 6) are LDR or Branch instruction No Yes Read the DataFlash into the internal SRAM. (code size to read in vector 6) Restore the reset value for the peripherals. Set the PC to 0 and perform the REMAP to jump to the downloaded application End 12.
SAM9G20 12.8 SDCard Boot The SDCard Boot program searches for a valid application in the SD Card memory. (Boot ROM does not support high capacity SDCards.) It looks for a boot.bin file in the root directory of a FAT12/16/32 formatted SDCard. If a valid file is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. This application may be the application code or a secondlevel bootloader. Note: 12.9 The bootable SDCard slot is Slot A.
SAM9G20 • Go (G): Jump to a specified address and execute the code - Address: Address to jump in hexadecimal - Output: ‘>’ • Get Version (V): Return the SAM-BA boot version - Output: ‘>’ 12.10.1 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115200 Baud, 8, n, 1. The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target.
SAM9G20 Microchip provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the document “USB Basic Application”, literature number 6123, for more details. 12.10.3.1 Enumeration Process The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification.
SAM9G20 12.11 Hardware and Software Constraints • The DataFlash, Serial Flash, NAND Flash, SDCard(1), and EEPROM downloaded code size must be inferior to 16K bytes. • The code is always downloaded from the device address 0x0000_0000 to the address 0x0000_0000 of the internal SRAM (after remap). • The downloaded code must be position-independent or linked at address 0x0000_0000. • The DataFlash must be connected to NPCS0 of the SPI. Note 1: Boot ROM does not support high capacity SDCards.
SAM9G20 13. Reset Controller (RSTC) 13.1 Overview The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 13.
SAM9G20 13.3.2 NRST Manager The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 13-2 shows the block diagram of the NRST Manager. Figure 13-2: NRST Manager RSTC_MR URSTIEN RSTC_SR URSTS NRSTL rstc_irq RSTC_MR URSTEN Other interrupt sources user_reset NRST RSTC_MR ERSTL nrst_out 13.3.2.1 External Reset Timer exter_nreset NRST Signal or Interrupt The NRST Manager samples the NRST pin at Slow Clock speed.
SAM9G20 Figure 13-3: BMS Sampling SLCK Core Supply POR output BMS Signal XXX H or L BMS sampling delay = 3 cycles proc_nreset 13.3.4 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. 13.3.4.1 General Reset A general reset occurs when VDDBU and VDDCORE are powered on.
SAM9G20 Figure 13-4: General Reset State SLCK Any Freq. MCK Backup Supply POR output Startup Time Main Supply POR output backup_nreset Processor Startup = 3 cycles proc_nreset RSTTYP XXX 0x0 = General Reset XXX periph_nreset NRST (nrst_out) BMS Sampling EXTERNAL RESET LENGTH = 2 cycles 13.3.4.2 Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset.
SAM9G20 Figure 13-5: Wake-up State SLCK Any Freq. MCK Main Supply POR output backup_nreset Resynch. 2 cycles proc_nreset RSTTYP Processor Startup = 3 cycles XXX 0x1 = WakeUp Reset XXX periph_nreset NRST (nrst_out) EXTERNAL RESET LENGTH = 4 cycles (ERSTL = 1) 13.3.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system.
SAM9G20 Figure 13-6: User Reset State SLCK MCK Any Freq. NRST Resynch. 2 cycles Resynch. 2 cycles Processor Startup = 3 cycles proc_nreset RSTTYP Any XXX 0x4 = User Reset periph_nreset NRST (nrst_out) >= EXTERNAL RESET LENGTH 13.3.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals.
SAM9G20 Figure 13-7: Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. 1 cycle Processor Startup = 3 cycles proc_nreset if PROCRST=1 RSTTYP Any XXX 0x3 = Software Reset periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) SRCMP in RSTC_SR 13.3.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles.
SAM9G20 Figure 13-8: Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 3 cycles proc_nreset RSTTYP Any XXX 0x2 = Watchdog Reset periph_nreset Only if WDRPROC = 0 NRST (nrst_out) EXTERNAL RESET LENGTH 8 cycles (ERSTL=2) 13.3.
SAM9G20 Figure 13-9: Reset Controller Status and Interrupt MCK read RSTC_SR Peripheral Access 2 cycle resynchronization 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) 2017 Microchip Technology Inc.
SAM9G20 13.4 Reset Controller (RSTC) User Interface Table 13-1: Register Mapping Offset Register Name Access Reset Value Backup Reset Value 0x00 Control Register RSTC_CR Write-only – – 0x04 Status Register RSTC_SR Read-only 0x0000_0001 0x0000_0000 0x08 Mode Register RSTC_MR Read/Write – 0x0000_0000 Note 1: The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. DS60001516A-page 88 2017 Microchip Technology Inc.
SAM9G20 13.4.1 Reset Controller Control Register Name:RSTC_CR Access:Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST PROCRST: Processor Reset 0: No effect. 1: If KEY is correct, resets the processor. PERRST: Peripheral Reset 0: No effect. 1: If KEY is correct, resets the peripherals. EXTRST: External Reset 0: No effect.
SAM9G20 13.4.2 Reset Controller Status Register Name:RSTC_SR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS URSTS: User Reset Status 0: No high-to-low edge on NRST happened since the last read of RSTC_SR. 1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.
SAM9G20 13.4.3 Reset Controller Mode Register Name:RSTC_MR Access:Read/Write 31 30 29 28 27 26 25 24 17 – 16 9 8 1 – 0 URSTEN KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 4 URSTIEN 3 – ERSTL 2 – URSTEN: User Reset Enable 0: The detection of a low level on the pin NRST does not generate a User Reset. 1: The detection of a low level on the pin NRST triggers a User Reset.
SAM9G20 14. Real-time Timer (RTT) 14.1 Overview The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt and/or triggers an alarm on a programmed value. 14.
SAM9G20 Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR.
SAM9G20 14.4 Real-time Timer (RTT) User Interface Table 14-1: Register Mapping Offset Register Name Access Reset 0x00 Mode Register RTT_MR Read/Write 0x0000_8000 0x04 Alarm Register RTT_AR Read/Write 0xFFFF_FFFF 0x08 Value Register RTT_VR Read-only 0x0000_0000 0x0C Status Register RTT_SR Read-only 0x0000_0000 DS60001516A-page 94 2017 Microchip Technology Inc.
SAM9G20 14.4.1 Real-time Timer Mode Register Name:RTT_MR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 RTTRST 17 RTTINCIEN 16 ALMIEN 15 14 13 12 11 10 9 8 3 2 1 0 RTPRES 7 6 5 4 RTPRES RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216. RTPRES ≠ 0: The prescaler period is equal to RTPRES.
SAM9G20 14.4.2 Real-time Timer Alarm Register Name:RTT_AR Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV ALMV: Alarm Value Defines the alarm value (ALMV+1) compared with the Real-time Timer. DS60001516A-page 96 2017 Microchip Technology Inc.
SAM9G20 14.4.3 Real-time Timer Value Register Name:RTT_VR Access:Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRTV 23 22 21 20 CRTV 15 14 13 12 CRTV 7 6 5 4 CRTV CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 2017 Microchip Technology Inc.
SAM9G20 14.4.4 Real-time Timer Status Register Name:RTT_SR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RTTINC 0 ALMS ALMS: Real-time Alarm Status 0: The Real-time Alarm has not occurred since the last read of RTT_SR. 1: The Real-time Alarm occurred since the last read of RTT_SR.
SAM9G20 15. Periodic Interval Timer (PIT) 15.1 Overview The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 15.2 Block Diagram Figure 15-1: Periodic Interval Timer PIT_MR PIV =? PIT_MR PITIEN set 0 PIT_SR pit_irq PITS reset 0 MCK Prescaler 15.
SAM9G20 The PIT is stopped when the core enters debug state. Figure 15-2: Enabling/Disabling PIT with PITEN APB cycle APB cycle MCK 15 restarts MCK Prescaler MCK Prescaler 0 PITEN CPIV PICNT 0 1 PIV - 1 0 PIV 1 0 1 0 PITS (PIT_SR) APB Interface read PIT_PIVR DS60001516A-page 100 2017 Microchip Technology Inc.
SAM9G20 15.4 Periodic Interval Timer (PIT) User Interface Table 15-1: Register Mapping Offset Register Name Access Reset 0x00 Mode Register PIT_MR Read/Write 0x000F_FFFF 0x04 Status Register PIT_SR Read-only 0x0000_0000 0x08 Periodic Interval Value Register PIT_PIVR Read-only 0x0000_0000 0x0C Periodic Interval Image Register PIT_PIIR Read-only 0x0000_0000 2017 Microchip Technology Inc.
SAM9G20 15.4.1 Periodic Interval Timer Mode Register Name:PIT_MR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 – 21 – 20 – 19 18 15 14 13 12 25 PITIEN 24 PITEN 17 16 PIV 11 10 9 8 3 2 1 0 PIV 7 6 5 4 PIV PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1).
SAM9G20 15.4.2 Periodic Interval Timer Status Register Name:PIT_SR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 PITS PITS: Periodic Interval Timer Status 0: The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1: The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. 2017 Microchip Technology Inc.
SAM9G20 15.4.3 Periodic Interval Timer Value Register Name:PIT_PIVR Access:Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV Reading this register clears PITS in PIT_SR. CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.
SAM9G20 15.4.4 Periodic Interval Timer Image Register Name:PIT_PIIR Access:Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 2017 Microchip Technology Inc.
SAM9G20 16. Watchdog Timer (WDT) 16.1 Overview The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 16.
SAM9G20 In normal operation, the user reloads the Watchdog at regular intervals before the timer underflow occurs, by writing the Control Register (WDT_CR) with the bit WDRSTT to 1. The Watchdog counter is then immediately reloaded from WDT_MR and restarted, and the Slow Clock 128 divider is reset and restarted. The WDT_CR is write-protected. As a result, writing WDT_CR without the correct hard-coded key has no effect.
SAM9G20 16.4 Watchdog Timer (WDT) User Interface Table 16-1: Register Mapping Offset Register Name Access Reset 0x00 Control Register WDT_CR Write-only – 0x04 Mode Register WDT_MR Read/Write Once 0x3FFF_2FFF 0x08 Status Register WDT_SR Read-only 0x0000_0000 DS60001516A-page 108 2017 Microchip Technology Inc.
SAM9G20 16.4.1 Watchdog Timer Control Register Name:WDT_CR Access:Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WDRSTT WDRSTT: Watchdog Restart 0: No effect. 1: Restarts the Watchdog. KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 2017 Microchip Technology Inc.
SAM9G20 16.4.2 Watchdog Timer Mode Register Name:WDT_MR Access: Read/Write Once 31 30 23 29 WDIDLEHLT 28 WDDBGHLT 27 21 20 19 18 11 10 22 26 25 24 17 16 9 8 1 0 WDD WDD 15 WDDIS 14 13 12 WDRPROC WDRSTEN WDFIEN 7 6 5 4 WDV 3 2 WDV WDV: Watchdog Counter Value Defines the value loaded in the 12-bit Watchdog Counter. WDFIEN: Watchdog Fault Interrupt Enable 0: A Watchdog fault (underflow or error) has no effect on interrupt.
SAM9G20 16.4.3 Watchdog Timer Status Register Name:WDT_SR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 WDERR 0 WDUNF WDUNF: Watchdog Underflow 0: No Watchdog underflow occurred since the last read of WDT_SR. 1: At least one Watchdog underflow occurred since the last read of WDT_SR.
SAM9G20 17. Shutdown Controller (SHDWC) 17.1 Overview The Shutdown Controller controls the power supplies VDDIO and VDDCORE and the wake-up detection on debounced input lines. 17.2 Block Diagram Figure 17-1: Shutdown Controller Block Diagram SLCK Shutdown Controller read SHDW_SR SHDW_MR CPTWK0 reset WAKEUP0 WKMODE0 SHDW_SR set WKUP0 read SHDW_SR Wake-up reset RTTWKEN SHDW_MR RTT Alarm RTTWK SHDW_SR set SHDW_CR SHDW 17.
SAM9G20 17.5 Functional Description The Shutdown Controller manages the main power supply. To do so, it is supplied with VDDBU and manages wake-up input pins and one output pin, SHDN. A typical application connects the pin SHDN to the shutdown input of the DC/DC Converter providing the main power supplies of the system, and especially VDDCORE and/or VDDIO. The wake-up inputs (WKUP0) connect to any push-buttons or signal that wake up the system.
SAM9G20 17.6 Shutdown Controller (SHDWC) User Interface Table 17-2: Register Mapping Offset Register Name Access Reset 0x00 Shutdown Control Register SHDW_CR Write-only – 0x04 Shutdown Mode Register SHDW_MR Read/Write 0x0000_0003 0x08 Shutdown Status Register SHDW_SR Read-only 0x0000_0000 DS60001516A-page 114 2017 Microchip Technology Inc.
SAM9G20 17.6.1 Shutdown Control Register Name:SHDW_CR Access:Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 SHDW SHDW: Shutdown Command 0: No effect. 1: If KEY is correct, asserts the SHDN pin. KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. 2017 Microchip Technology Inc.
SAM9G20 17.6.2 Shutdown Mode Register Name:SHDW_MR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 RTTWKEN 15 14 13 12 11 – 10 – 9 3 – 2 – 1 CPTWK1 7 6 5 4 CPTWK0 8 – 0 WKMODE0 WKMODE0: Wake-up Mode 0 WKMODE[1:0] Wake-up Input Transition Selection 0 0 None.
SAM9G20 17.6.3 Shutdown Status Register Name:SHDW_SR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 RTTWK 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 WAKEUP0 WAKEUP0: Wake-up 0 Status 0: No wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR. 1: At least one wake-up event occurred on the corresponding wake-up input since the last read of SHDW_SR.
SAM9G20 18. SAM9G20 Bus Matrix 18.1 Overview The Bus Matrix implements a multi-layer AHB based on the AHB-Lite protocol that enables parallel access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The Bus Matrix interconnects 6 AHB Masters to 5 AHB Slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle latency).
SAM9G20 18.4.1 Arbitration Rules Each arbiter has the ability to arbitrate between two or more different master’s requests. In order to avoid burst breaking and also to provide the maximum throughput for slave interfaces, arbitration may only take place during the following cycles: 1. 2. 3. 4. Idle Cycles: when a slave is not connected to any master or is connected to a master which is not currently accessing it. Single Cycles: when a slave is currently doing a single access.
SAM9G20 18.4.3 Fixed Priority Arbitration This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using the fixed priority defined by the user. If two or more master’s requests are active at the same time, the master with the highest priority number is serviced first. If two or more master’s requests with the same priority are active at the same time, the master with the highest number is serviced first.
SAM9G20 18.
SAM9G20 18.5.1 Bus Matrix Master Configuration Registers Name:MATRIX_MCFG0...
SAM9G20 18.5.2 Bus Matrix Slave Configuration Registers Name:MATRIX_SCFG0...MATRIX_SCFG4 Access:Read/Write 31 30 29 28 27 26 – – – – – – 23 22 21 20 19 18 – FIXED_DEFMSTR 25 24 ARBT 17 16 DEFMSTR_TYPE 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SLOT_CYCLE SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
SAM9G20 18.5.3 Bus Matrix Priority Registers For Slaves Name:MATRIX_PRAS0...MATRIX_PRAS4 Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – 15 14 11 10 – – – – 7 6 3 2 – – – – M5PR 13 12 M3PR 5 4 M1PR 16 M4PR 9 8 M2PR 1 0 M0PR MxPR: Master x Priority Fixed priority of Master x for access to the selected slave. The higher the number, the higher the priority. DS60001516A-page 124 2017 Microchip Technology Inc.
SAM9G20 18.5.4 Bus Matrix Master Remap Control Register Name:MATRIX_MRCR Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – RCB1 RCB0 RCBx: Remap Command Bit for AHB Master x 0: Disable remapped address decoding for the selected Master 1: Enable remapped address decoding for the selected Master 2017 Microchip Technology Inc.
SAM9G20 18.6 Chip Configuration User Interface Table 18-2: Register Mapping Offset Register Name Access Reset 0x0110–0x0118 Reserved – – – EBI_CSA Read/Write 0x00010000 – – – 0x011C 0x0130–0x01FC EBI Chip Select Assignment Register Reserved DS60001516A-page 126 2017 Microchip Technology Inc.
SAM9G20 18.6.1 EBI Chip Select Assignment Register Name:EBI_CSA Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – IOSR VDDIOMSEL 15 14 13 12 11 10 9 8 – – – – – – – EBI_DBPUC 7 6 5 4 3 2 1 0 – – EBI_CS5A EBI_CS4A EBI_CS3A – EBI_CS1A – EBI_CS1A: EBI Chip Select 1 Assignment 0: EBI Chip Select 1 is assigned to the Static Memory Controller. 1: EBI Chip Select 1 is assigned to the SDRAM Controller.
SAM9G20 19. SAM9G20 External Bus Interface 19.1 Overview The External Bus Interface (EBI) is designed to ensure the successful data transfer between several external devices and the embedded Memory Controller of an Arm-based device. The Static Memory, SDRAM and ECC Controllers are all featured external Memory Controllers on the EBI. These external Memory Controllers are capable of handling several types of external memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, and SDRAM.
SAM9G20 Figure 19-1: Organization of the External Bus Interface D[15:0] External Bus Interface Bus Matrix A0/NBS0 AHB A1/NWR2/NBS2 SDRAM Controller A[15:2], A[20:18] A16/BA0 A17/BA1 MUX Logic Static Memory Controller NCS0 NCS1/SDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK SDCKE CompactFlash Logic RAS CAS SDWE SDA10 NAND Flash Logic A21/NANDALE A22/NANDCLE NANDOE NANDWE ECC Controller NCS3/NANDCS D[31:16] PIO Address Decoders Chip Select Assignor A[24:23] A25/CFRNW NCS4/C
SAM9G20 19.
SAM9G20 Table 19-2 details the connections between the two memory controllers and the EBI pins. Table 19-2: 19.
SAM9G20 Table 19-3: EBI Pins and External Static Devices Connections (Continued) Pins of the SMC Interfaced Device Signals: EBI_ NWR0/NWE 8-bit Static Device 2 x 8-bit Static Devices 16-bit Static Device 4 x 8-bit Static Devices 2 x 16-bit Static Devices 32-bit Static Device WE WE(1) WE WE(2) WE WE NWR1/NBS1 – WE NWR3/NBS3 – – (1) NUB WE (2) BE1(5) NUB(4) BE3(5) NUB WE(2) – (3) Note 1: NWR1 enables upper byte writes. NWR0 enables lower byte writes.
SAM9G20 Table 19-4: EBI Pins and External Device Connections (Continued) Pins of the Interfaced Device SDRAM Controller Static Memory Controller SDRAM CompactFlash (EBI only) CompactFlash True IDE Mode (EBI only) NAND Flash NCS3/NANDCS – – – CE(3) NCS4/CFCS0 – CFCS0(1) CFCS0(1) – NCS5/CFCS1 – CFCS1(1) CFCS1(1) – NCS6 – – – – NCS7 – – – – NANDOE – – – RE NANDWE – – – WE NRD/CFOE – OE – – NWR0/NWE/CFWE – WE WE – NWR1/NBS1/CFIOR DQM1 IOR IOR – NWR3/NBS3/
SAM9G20 19.4.2 Connection Examples Figure 19-2 shows an example of connections between the EBI and external devices.
SAM9G20 19.6.1 Bus Multiplexing The EBI offers a complete set of control signals that share the 32-bit data lines, the address lines of up to 26 bits and the control signals through a multiplex logic operating in function of the memory area requests. Multiplexing is specifically organized in order to guarantee the maintenance of the address and output control lines at a stable state while no external access is being performed.
SAM9G20 Figure 19-3: CompactFlash Memory Mapping True IDE Alternate Mode Space Offset 0x00E0 0000 True IDE Mode Space Offset 0x00C0 0000 CF Address Space I/O Mode Space Offset 0x0080 0000 Common Memory Mode Space Offset 0x0040 0000 Attribute Memory Mode Space Offset 0x0000 0000 Note: The A22 pin is used to drive the REG signal of the CompactFlash Device (except in True IDE mode).
SAM9G20 Table 19-6: CFCE1 and CFCE2 Truth Table (Continued) Mode CFCE2 CFCE1 DBW Comment SMC Access Mode Task File 1 0 8 bits Data Register 1 0 16 bits 0 1 Don’t Care Access to Even Byte on D[7:0] 0 1 8 bits Access to Odd Byte on D[7:0] 1 1 – True IDE Mode Access to Even Byte on D[7:0] Access to Odd Byte on D[7:0] Access to Even Byte on D[7:0] Access to Odd Byte on D[15:8] Byte Select Alternate True IDE Mode Control Register Alternate Status Read Drive Address Standby Mode or Ad
SAM9G20 19.6.6.4 Multiplexing of CompactFlash Signals on EBI Pins Table 19-8 and Table 19-9 illustrate the multiplexing of the CompactFlash logic signals with other EBI signals on the EBI pins. The EBI pins in Table 19-8 are strictly dedicated to the CompactFlash interface as soon as the EBI_CS4A and/or EBI_CS5A bit(s) in the EBI_CSA register is/are set. These pins must not be used to drive any other memory devices.
SAM9G20 Figure 19-5: CompactFlash Application Example EBI CompactFlash Connector D[15:0] D[15:0] DIR /OE A25/CFRNW NCS4/CFCS0 _CD1 CD (PIO) _CD2 /OE 19.6.7 A[10:0] A[10:0] A22/REG _REG NOE/CFOE _OE NWE/CFWE _WE NWR1/CFIOR _IORD NWR3/CFIOW _IOWR CFCE1 _CE1 CFCE2 _CE2 NWAIT _WAIT NAND Flash Support The External Bus Interface integrates circuitry that interfaces to NAND Flash devices. 19.6.7.
SAM9G20 Figure 19-6: NAND Flash Signal Multiplexing on EBI Pins SMC NAND Flash Logic NANDOE NCSx NRD_NOE NANDWE NANDOE NANDWE NWR0_NWE 19.6.7.2 NAND Flash Signals The address latch enable and command latch enable signals on the NAND Flash device are driven by address bits A22 and A21 of the EBI address bus. The command, address or data words on the data bus of the NAND Flash device are distinguished by using their address within the NCSx address space.
SAM9G20 19.7 Implementation Examples The following hardware configurations are given for illustration only. The user should refer to the memory manufacturer website to check current device availability. 19.7.1 16-bit SDRAM Figure 19-8: Hardware Configuration - 16-bit SDRAM D[0..15] A[0..
SAM9G20 19.7.2 19.7.2.1 32-bit SDRAM Hardware Configuration - 32-bit SDRAM D[0..31] A[0..14] U1 (Not used A12) A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A13 SDA10 BA0 BA1 SDA10 BA0 BA1 A14 23 24 25 26 29 30 31 32 33 34 22 35 20 21 36 40 SDCKE SDCK A0 CFIOR_NBS1_NWR1 CAS RAS SDWE SDCS_NCS1 SDCKE 37 SDCK 38 1%6 1%6 15 39 CAS RAS 17 18 SDWE 16 19 U2 A0 MT48LC16M16A2 DQ0 A1 DQ1 A2 DQ2 A3 DQ3 A4 DQ4 A5 DQ5 A6 DQ6 A7 DQ7 A8 DQ8 A9 DQ9 A10 DQ10 A11 DQ11 DQ12 BA0 DQ13 BA1 DQ14 DQ15 A12 N.
SAM9G20 19.7.3 8-bit NAND Flash Figure 19-9: Hardware Configuration - 8-bit NAND Flash D[0..7] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) R1 3V3 R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 10K 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 25 26 K9F2G08U0M N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 29 30 31 32 41 42 43 44 N.C N.C N.C N.C N.C N.C PRE N.C N.C N.C N.C N.
SAM9G20 19.7.4 16-bit NAND Flash Figure 19-10: Hardware Configuration - 16-bit NAND Flash D[0..15] U1 CLE ALE NANDOE NANDWE (ANY PIO) (ANY PIO) R1 3V3 R2 10K 16 17 8 18 9 CLE ALE RE WE CE 7 R/B 19 WP 1 2 3 4 5 6 10 11 14 15 20 21 22 23 24 34 35 N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C N.C 10K MT29F2G16AABWP-ET I/O0 26 I/O1 28 I/O2 30 I/O3 32 I/O4 40 I/O5 42 I/O6 44 I/O7 46 I/O8 27 I/O9 29 I/O10 31 I/O11 33 I/O12 41 I/O13 43 I/O14 45 I/O15 47 N.C PRE N.
SAM9G20 19.7.5 NOR Flash on NCS0 Figure 19-11: Hardware Configuration - NOR Flash on NCS0 D[0..15] A[1..
SAM9G20 19.7.6 19.7.6.1 Compact Flash Hardware Configuration - Compact Flash MEMORY & I/O MODE D[0..
SAM9G20 19.7.6.2 Software Configuration - Compact Flash The following configuration has to be performed: • Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located in the bus matrix memory space. • The address line A23 is to select I/O (A23 = 1) or Memory mode (A23 = 0) and the address line A22 for REG function.
SAM9G20 19.7.7 19.7.7.1 Compact Flash True IDE Hardware Configuration - Compact Flash True IDE TRUE IDE MODE D[0..
SAM9G20 19.7.7.2 Software Configuration - Compact Flash True IDE The following configuration has to be performed: • Assign the EBI CS4 and/or EBI_CS5 to the CompactFlash Slot 0 or/and Slot 1 by setting the bit EBI_CS4A or/and EBI_CS5A in the EBI Chip Select Assignment Register located in the bus matrix memory space. • The address line A21 is to select Alternate True IDE (A21 = 1) or True IDE (A21 = 0) modes.
SAM9G20 20. Static Memory Controller (SMC) 20.1 Overview The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or peripheral devices. It has 8 Chip Selects and a 26-bit address bus. The 32-bit data bus can be configured to interface with 8-, 16-, or 32-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully parametrizable.
SAM9G20 20.4 20.4.1 Application Example Hardware Interface Figure 20-1: SMC Connections to Static Memory Devices D0-D31 A0/NBS0 NWR0/NWE NWR1/NBS1 A1/NWR2/NBS2 NWR3/NBS3 D0 - D7 128K x 8 SRAM D8-D15 D0 - D7 CS NRD NWR0/NWE A2 - A25 A2 - A18 A0 - A16 NRD OE NWR1/NBS1 WE 128K x 8 SRAM D16 - D23 D24-D31 D0 - D7 A0 - A16 NRD Static Memory Controller 20.5 20.5.
SAM9G20 20.6 External Memory Mapping The SMC provides up to 26 address lines, A[25:0]. This allows each chip select line to address up to 64 Mbytes of memory. If the physical memory device connected on one chip select is smaller than 64 Mbytes, it wraps around and appears to be repeated within this space. The SMC correctly handles any valid access to the memory device within the page (see Figure 20-2).
SAM9G20 Figure 20-4: Memory Connection for a 16-bit Data Bus D[15:0] D[15:0] A[19:2] A[18:1] A1 SMC Low Byte Enable NBS1 High Byte Enable NWE Write Enable NRD Output Enable NCS[2] Figure 20-5: Memory Enable Memory Connection for a 32-bit Data Bus D[31:16] SMC D[31:16] D[15:0] D[15:0] A[20:2] A[18:0] NBS0 Byte 0 Enable NBS1 Byte 1 Enable NBS2 Byte 2 Enable NBS3 Byte 3 Enable NWE Write Enable NRD Output Enable NCS[2] 20.7.2.
SAM9G20 Figure 20-6: Connection of 2 x 8-bit Devices on a 16-bit Bus: Byte Write Option D[7:0] D[7:0] D[15:8] A[24:2] SMC A1 NWR0 A[23:1] A[0] Write Enable NWR1 NRD NCS[3] Read Enable Memory Enable D[15:8] A[23:1] A[0] Write Enable Read Enable Memory Enable 20.7.2.3 Signal Multiplexing Depending on the BAT, only the write signals or the byte select signals are used. To save IOs at the external bus interface, control signals at the SMC interface are multiplexed.
SAM9G20 Figure 20-7: Connection of 2x16-bit Data Bus on a 32-bit Data Bus (Byte Select Option) D[15:0] D[15:0] D[31:16] A[25:2] SMC A[23:0] NWE Write Enable NBS0 Low Byte Enable NBS1 High Byte Enable NBS2 NBS3 Read Enable NRD Memory Enable NCS[3] D[31:16] A[23:0] Write Enable Low Byte Enable High Byte Enable Read Enable Memory Enable Table 20-3: SMC Multiplexed Signal Translation Signal Name 32-bit Bus Device Type 16-bit Bus 8-bit Bus 1x32-bit 2x16-bit 4 x 8-bit 1x16-bit 2 x 8-bi
SAM9G20 20.8.1 Read Waveforms The read cycle is shown on Figure 20-8. The read cycle starts with the address setting on the memory address bus, i.e.: {A[25:2], A1, A0} for 8-bit devices {A[25:2], A1} for 16-bit devices A[25:2] for 32-bit devices. Figure 20-8: Standard Read Cycle MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NRD NCS D[31:0] NRD_SETUP NCS_RD_SETUP NRD_PULSE NCS_RD_PULSE NRD_HOLD NCS_RD_HOLD NRD_CYCLE 20.8.1.
SAM9G20 All NRD and NCS timings are defined separately for each chip select as an integer number of Master Clock cycles. To ensure that the NRD and NCS timings are coherent, user must define the total read cycle instead of the hold timing. NRD_CYCLE implicitly defines the NRD hold time and NCS hold time as: NRD_HOLD = NRD_CYCLE - NRD SETUP - NRD PULSE NCS_RD_HOLD = NRD_CYCLE - NCS_RD_SETUP - NCS_RD_PULSE 20.8.1.
SAM9G20 Figure 20-10: READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD MCK A[25:2] NBS0,NBS1, NBS2,NBS3, A0, A1 NRD NCS tPACC D[31:0] Data Sampling 20.8.2.2 Read is Controlled by NCS (READ_MODE = 0) Figure 20-11 shows the typical read cycle of an LCD module. The read data is valid tPACC after the falling edge of the NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised.
SAM9G20 20.8.3 Write Waveforms The write protocol is similar to the read protocol. It is depicted in Figure 20-12. The write cycle starts with the address setting on the memory address bus. 20.8.3.1 NWE Waveforms The NWE signal is characterized by a setup timing, a pulse width and a hold timing. 1. 2. 3.
SAM9G20 20.8.3.4 Null Delay Setup and Hold If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of consecutive write cycles in the same memory (see Figure 20-13). However, for devices that perform write operations on the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed.
SAM9G20 Figure 20-14: WRITE_MODE = 1. The write operation is controlled by NWE MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE, NWR0, NWR1, NWR2, NWR3 NCS D[31:0] 20.8.4.2 Write is Controlled by NCS (WRITE_MODE = 0) Figure 20-15 shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during the pulse and hold steps of the NCS signal.
SAM9G20 Table 20-4 shows how the timing parameters are coded and their permitted range. Table 20-4: Coding and Range of Timing Parameters Permitted Range Coded Value Number of Bits Effective Value Coded Value Effective Value setup [5:0] 6 128 x setup[5] + setup[4:0] 0 ≤ 31 128 ≤ 128 + 31 pulse [6:0] 7 256 x pulse[6] + pulse[5:0] 0 ≤ 63 256 ≤ 256 + 63 cycle [8:0] 9 256 x cycle[8:7] + cycle[6:0] 0 ≤ 127 512 ≤ 512 + 127 256 ≤ 256 + 127 768 ≤ 768 + 127 20.8.
SAM9G20 Figure 20-16: Chip Select Wait State between a Read Access on NCS0 and a Write Access on NCS2 MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NWE NCS0 NCS2 NRD_CYCLE NWE_CYCLE D[31:0] Read to Write Chip Select Wait State Wait State 20.9.2 Early Read Wait State In some cases, the SMC inserts a wait state cycle between a write access and a read access to allow time for the write cycle to end before the subsequent read cycle begins.
SAM9G20 Figure 20-17: Early Read Wait State: Write with No Hold Followed by Read with No Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 NWE NRD no hold no setup D[31:0] write cycle Figure 20-18: Early Read wait state read cycle Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read, No NCS Setup MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NCS NRD no hold no setup D[31:0] write cycle (WRITE_MODE = 0) DS60001516A-page 164 Early Read wait state read cycle (READ_MODE = 0 or
SAM9G20 Figure 20-19: Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read, 1 Set-up Cycle MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 internal write controlling signal external write controlling signal (NWE) no hold read setup = 1 NRD D[31:0] write cycle (WRITE_MODE = 1) 20.9.3 Early Read wait state read cycle (READ_MODE = 0 or READ_MODE = 1) Reload User Configuration Wait State The user may change any of the configuration parameters by writing the SMC user interface.
SAM9G20 20.10 Data Float Wait States Some memory devices are slow to release the external bus. For such devices, it is necessary to add wait states (data float wait states) after a read access: • before starting a read access to a different external memory • before starting a write access to the same device or to a different external one. The Data Float Output Time (tDF) for each external memory device is programmed in the TDF_CYCLES field of the SMC_MODE register for the corresponding chip select.
SAM9G20 Figure 20-21: TDF Period in NCS Controlled Read Operation (TDF = 3) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NRD NCS tpacc D[31:0] TDF = 3 clock cycles NCS controlled read operation 20.10.2 TDF Optimization Enabled (TDF_MODE = 1) When the TDF_MODE of the SMC_MODE register is set to 1 (TDF optimization is enabled), the SMC takes advantage of the setup period of the next access to optimize the number of wait states cycle to insert.
SAM9G20 Figure 20-22: TDF Optimization: No TDF wait states are inserted if the TDF period is over when the next access begins MCK A[25:2] NRD NRD_HOLD= 4 NWE NWE_SETUP= 3 NCS0 TDF_CYCLES = 6 D[31:0] read access on NCS0 (NRD controlled) 20.10.
SAM9G20 Figure 20-23: TDF Optimization Disabled (TDF Mode = 0).
SAM9G20 Figure 20-25: TDF Mode = 0: TDF wait states between read and write accesses on the same chip select MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0, A1 read1 controlling signal (NRD) write2 setup = 1 read1 hold = 1 write2 controlling signal (NWE) TDF_CYCLES = 5 D[31:0] 4 TDF WAIT STATES read1 cycle TDF_CYCLES = 5 Read to Write Wait State write2 cycle TDF_MODE = 0 (optimization disabled) 20.11 External Wait Any access can be extended by an external device using the NWAIT input signal of the SMC.
SAM9G20 Figure 20-26: Write Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 FROZEN STATE 4 3 2 1 1 1 1 0 3 2 2 2 2 1 NWE 6 5 4 0 NCS D[31:0] NWAIT internally synchronized NWAIT signal Write cycle EXNW_MODE = 10 (Frozen) WRITE_MODE = 1 (NWE_controlled) NWE_PULSE = 5 NCS_WR_PULSE = 7 2017 Microchip Technology Inc.
SAM9G20 Figure 20-27: Read Access with NWAIT Assertion in Frozen Mode (EXNW_MODE = 10) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NCS FROZEN STATE 4 1 NRD 3 2 2 2 1 0 2 1 0 2 1 0 0 5 5 5 4 3 NWAIT internally synchronized NWAIT signal Read cycle EXNW_MODE = 10 (Frozen) READ_MODE = 0 (NCS_controlled) NRD_PULSE = 2, NRD_HOLD = 6 NCS_RD_PULSE =5, NCS_RD_HOLD =3 DS60001516A-page 172 Assertion is ignored 2017 Microchip Technology Inc.
SAM9G20 20.11.3 Ready Mode In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined. If asserted, the SMC suspends the access as shown in Figure 20-28 and Figure 20-29. After deassertion, the access is completed: the hold step of the access is performed.
SAM9G20 Figure 20-29: NWAIT Assertion in Read Access: Ready Mode (EXNW_MODE = 11) MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 Wait STATE 6 5 4 3 2 1 0 0 6 5 4 3 2 1 1 NCS NRD 0 NWAIT internally synchronized NWAIT signal Read cycle EXNW_MODE = 11(Ready mode) READ_MODE = 0 (NCS_controlled) Assertion is ignored Assertion is ignored NRD_PULSE = 7 NCS_RD_PULSE =7 DS60001516A-page 174 2017 Microchip Technology Inc.
SAM9G20 20.11.4 NWAIT Latency and Read/Write Timings There may be a latency between the assertion of the read/write controlling signal and the assertion of the NWAIT signal by the device. The programmed pulse length of the read/write controlling signal must be at least equal to this latency plus the 2 cycles of resynchronization + 1 cycle. Otherwise, the SMC may enter the hold state of the access without detecting the NWAIT signal assertion. This is true in frozen mode as well as in ready mode.
SAM9G20 20.12 Slow Clock Mode The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when an internal signal driven by the Power Management Controller is asserted because MCK has been turned to a very slow clock rate (typically 32 kHz clock rate). In this mode, the user-programmed waveforms are ignored and the slow clock mode waveforms are applied. This mode is provided so as to avoid reprogramming the User Interface with appropriate waveforms at very slow clock rate.
SAM9G20 Figure 20-32: Clock Rate Transition Occurs while the SMC is Performing a Write Operation Slow Clock Mode internal signal from PMC MCK A[25:2] NBS0, NBS1, NBS2, NBS3, A0,A1 NWE 1 1 1 1 1 1 3 2 2 NCS NWE_CYCLE = 3 NWE_CYCLE = 7 SLOW CLOCK MODE WRITE SLOW CLOCK MODE WRITE This write cycle finishes with the slow clock mode set of parameters after the clock rate transition Figure 20-33: NORMAL MODE WRITE Slow clock mode transition is detected: Reload Configuration Wait State Recommend
SAM9G20 20.13 Asynchronous Page Mode The SMC supports asynchronous burst reads in page mode, providing that the page mode is enabled in the SMC_MODE register (PMEN field). The page size must be configured in the SMC_MODE register (PS field) to 4, 8, 16 or 32 bytes. The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte page) is always aligned to 4-byte boundaries (resp. 8-, 16-, 32-byte boundaries) of memory.
SAM9G20 Table 20-7: Programming of Read Timings in Page Mode Parameter Value Definition READ_MODE ‘x’ No impact NCS_RD_SETUP ‘x’ No impact NCS_RD_PULSE tpa Access time of first access to the page NRD_SETUP ‘x’ No impact NRD_PULSE tsa Access time of subsequent accesses in the page NRD_CYCLE ‘x’ No impact The SMC does not check the coherency of timings.
SAM9G20 Figure 20-35: Access to Non-sequential Data within the Same Page MCK Page address A[25:3] A[2], A1, A0 A1 A3 A7 NRD NCS D[7:0] D1 NCS_RD_PULSE DS60001516A-page 180 D3 NRD_PULSE D7 NRD_PULSE 2017 Microchip Technology Inc.
SAM9G20 20.14 Static Memory Controller (SMC) User Interface The SMC is programmed using the registers listed in Table 20-8. For each chip select, a set of 4 registers is used to program the parameters of the external device connected on it. In Table 20-8, “CS_number” denotes the chip select number. 16 bytes (0x10) are required per chip select. The user must complete writing the configuration by writing any one of the SMC_MODE registers.
SAM9G20 20.14.1 SMC Setup Register Name:SMC_SETUP[0 ..
SAM9G20 20.14.2 SMC Pulse Register Name:SMC_PULSE[0..7] Access:Read/Write 31 30 29 28 27 – 23 22 21 20 19 – 15 25 24 18 17 16 10 9 8 2 1 0 NRD_PULSE 14 13 12 – 7 26 NCS_RD_PULSE 11 NCS_WR_PULSE 6 5 4 – 3 NWE_PULSE NWE_PULSE: NWE Pulse Length The NWE signal pulse length is defined as: NWE pulse length = (256* NWE_PULSE[6] + NWE_PULSE[5:0]) clock cycles The NWE pulse length must be at least 1 clock cycle.
SAM9G20 20.14.3 SMC Cycle Register Name:SMC_CYCLE[0..7] Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – NRD_CYCLE 23 22 21 20 19 18 17 16 NRD_CYCLE 15 14 13 12 11 10 9 8 – – – – – – – NWE_CYCLE 7 6 5 4 3 2 1 0 NWE_CYCLE NWE_CYCLE: Total Write Cycle Length The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pulse and hold steps of the NWE and NCS signals.
SAM9G20 20.14.4 SMC MODE Register Name:SMC_MODE[0..7] Access:Read/Write 31 30 – – 29 28 23 22 21 20 – – – TDF_MODE 15 14 13 – – 7 6 – – PS 12 DBW 5 4 EXNW_MODE 27 26 25 24 – – – PMEN 19 18 17 16 TDF_CYCLES 11 10 9 8 – – – BAT 3 2 1 0 – – WRITE_MODE READ_MODE READ_MODE: 1: The read operation is controlled by the NRD signal. – If TDF cycles are programmed, the external bus is marked busy after the rising edge of NRD.
SAM9G20 BAT: Byte Access Type This field is used only if DBW defines a 16- or 32-bit data bus. • 1: Byte write access type: – Write operation is controlled using NCS, NWR0, NWR1, NWR2, NWR3. – Read operation is controlled using NCS and NRD.
SAM9G20 21. SDRAM Controller (SDRAMC) 21.1 Overview The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the interface to an external 16-bit or 32-bit SDRAM device. The page size supports ranges from 2048 to 8192 and the number of columns from 256 to 2048. It supports byte (8-bit), half-word (16-bit) and word (32-bit) accesses. The SDRAM Controller supports a read or write burst length of one location.
SAM9G20 21.3.1.
SAM9G20 21.3.1.
SAM9G20 21.4 21.4.1 Product Dependencies SDRAM Device Initialization The initialization sequence is generated by software. The SDRAM devices are initialized by the following sequence: 1. SDRAM features must be set in the configuration register: asynchronous timings (TRC, TRAS, etc.), number of columns, rows, CAS latency, and the data bus width. 2. For mobile SDRAM, temperature-compensated self refresh (TCSR), drive strength (DS) and partial array self refresh (PASR) must be set in the Low Power Register.
SAM9G20 Figure 21-1: SDRAM Device Initialization Sequence SDCKE tRP tRC tMRD SDCK SDRAMC_A[9:0] A10 SDRAMC_A[12:11] SDCS RAS CAS SDWE NBS Inputs Stable for 200 μsec 21.4.2 Precharge All Banks 1st Auto-refresh 8th Auto-refresh MRS Command Valid Command I/O Lines The pins used for interfacing the SDRAM Controller may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the SDRAM Controller pins to their peripheral function.
SAM9G20 Figure 21-2: Write Burst, 32-bit SDRAM Access tRCD = 3 SDCS SDCK SDRAMC_A[12:0] Row n col a col b col c col d col e col f col g col h col i col j col k col l Dnb Dnc Dnd Dne Dnf Dng Dnh Dni Dnj Dnk Dnl RAS CAS SDWE D[31:0] 21.5.2 Dna SDRAM Controller Read Cycle The SDRAM Controller allows burst access, incremental burst of unspecified length or single access.
SAM9G20 Figure 21-3: Read Burst, 32-bit SDRAM Access tRCD = 3 CAS = 2 SDCS SDCK SDRAMC_A[12:0] Row n col a col b col c col d col e col f RAS CAS SDWE D[31:0] (Input) 21.5.3 Dna Dnb Dnc Dne Dnd Dnf Border Management When the memory row boundary has been reached, an automatic page break is inserted. In this case, the SDRAM controller generates a precharge command, activates the new row and initiates a read or write command.
SAM9G20 21.5.4 SDRAM Controller Refresh Cycles An auto-refresh command is used to refresh the SDRAM device. Refresh addresses are generated internally by the SDRAM device and incremented after each auto-refresh automatically. The SDRAM Controller generates these auto-refresh commands periodically. An internal timer is loaded with the value in the register SDRAMC_TR that indicates the number of clock cycles between refresh cycles.
SAM9G20 Figure 21-6: Self-refresh Mode Behavior Self Refresh Mode TXSR = 3 SRCB = 1 Write SDRAMC_SRR Row SDRAMC_A[12:0] SDCK SDCKE SDCS RAS CAS SDWE Access Request to the SDRAM Controller 21.5.5.2 Low-power Mode This mode is selected by programming the LPCB field to 2 in the SDRAMC Low Power Register. Power consumption is greater than in self-refresh mode. All the input and output buffers of the SDRAM device are deactivated except SDCKE, which remains low.
SAM9G20 Figure 21-7: Low-power Mode Behavior TRCD = 3 CAS = 2 Low Power Mode SDCS SDCK SDRAMC_A[12:0] Row n col a col b col c col d col e col f RAS CAS SDCKE D[31:0] (input) 21.5.5.3 Dna Dnb Dnc Dnd Dne Dnf Deep Power-down Mode This mode is selected by programming the LPCB field to 3 in the SDRAMC Low Power Register. When this mode is activated, all internal voltage generators inside the SDRAM are stopped and all data is lost.
SAM9G20 Figure 21-8: Deep Power-down Mode Behavior tRP = 3 SDCS SDCK Row n SDRAMC_A[12:0] col c col d RAS CAS SDWE CKE D[31:0] (input) 2017 Microchip Technology Inc.
SAM9G20 21.
SAM9G20 21.6.1 SDRAMC Mode Register Name:SDRAMC_MR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 1 0 MODE MODE: SDRAMC Command Mode This field defines the command issued by the SDRAM Controller when the SDRAM device is accessed. MODE Description 0 0 0 Normal mode. Any access to the SDRAM is decoded normally.
SAM9G20 21.6.2 SDRAMC Refresh Timer Register Name:SDRAMC_TR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 3 1 0 COUNT 2 COUNT COUNT: SDRAMC Refresh Timer Count This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst is initiated.
SAM9G20 21.6.3 SDRAMC Configuration Register Name:SDRAMC_CR Access:Read/Write 31 30 29 28 27 26 TXSR 23 22 21 20 19 18 TRCD 15 24 17 16 9 8 1 0 TRP 14 13 12 11 10 TRC 7 DBW 25 TRAS TWR 6 5 CAS 4 NB 3 2 NR NC NC: Number of Column Bits Reset value is 8 column bits. NC Column Bits 0 0 8 0 1 9 1 0 10 1 1 11 NR: Number of Row Bits Reset value is 11 row bits. NR Row Bits 0 0 11 0 1 12 1 0 13 1 1 Reserved NB: Number of Banks Reset value is two banks.
SAM9G20 CAS: CAS Latency Reset value is two cycles. In the SDRAMC, only a CAS latency of one, two and three cycles are managed. CAS CAS Latency (Cycles) 0 0 Reserved 0 1 1 1 0 2 1 1 3 DBW: Data Bus Width Reset value is 16 bits 0: Data bus width is 32 bits. 1: Data bus width is 16 bits. TWR: Write Recovery Delay Reset value is two cycles. This field defines the Write Recovery Time in number of cycles. Number of cycles is between 0 and 15. TRC: Row Cycle Delay Reset value is seven cycles.
SAM9G20 21.6.4 SDRAMC Low Power Register Name:SDRAMC_LPR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 12 11 10 9 7 – 6 5 PASR TIMEOUT DS 4 3 – 8 TCSR 2 – 1 0 LPCB LPCB: Low-power Configuration Bits 00 Low Power Feature is inhibited: no Power-down, Self-refresh or Deep Power-down command is issued to the SDRAM device.
SAM9G20 21.6.5 SDRAMC Interrupt Enable Register Name:SDRAMC_IER Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES RES: Refresh Error Status 0: No effect. 1: Enables the refresh error interrupt. DS60001516A-page 204 2017 Microchip Technology Inc.
SAM9G20 21.6.6 SDRAMC Interrupt Disable Register Name:SDRAMC_IDR Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES RES: Refresh Error Status 0: No effect. 1: Disables the refresh error interrupt. 2017 Microchip Technology Inc.
SAM9G20 21.6.7 SDRAMC Interrupt Mask Register Name:SDRAMC_IMR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES RES: Refresh Error Status 0: The refresh error interrupt is disabled. 1: The refresh error interrupt is enabled. DS60001516A-page 206 2017 Microchip Technology Inc.
SAM9G20 21.6.8 SDRAMC Interrupt Status Register Name:SDRAMC_ISR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RES RES: Refresh Error Status 0: No refresh error has been detected since the register was last read. 1: A refresh error has been detected since the register was last read. 2017 Microchip Technology Inc.
SAM9G20 21.6.9 SDRAMC Memory Device Register Name:SDRAMC_MDR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 0 MD MD: Memory Device Type 00 SDRAM 01 Low-power SDRAM 10 Reserved 11 Reserved. DS60001516A-page 208 2017 Microchip Technology Inc.
SAM9G20 22. Error Correction Code Controller (ECC) 22.1 Overview NAND Flash/SmartMedia devices contain by default invalid blocks which have one or more invalid bits. Over the NAND Flash/SmartMedia lifetime, additional invalid blocks may occur which can be detected/corrected by ECC code. The ECC Controller is a mechanism that encodes data in a manner that makes possible the identification and correction of certain errors in data.
SAM9G20 ECC is automatically computed as soon as a read (00h)/write (80h) command to the NAND Flash or the SmartMedia is detected. Read and write access must start at a page boundary. ECC results are available as soon as the counter reaches the end of the main area. Values in the ECC Parity Registers (ECC_PR0 to ECC_PR15) are then valid and locked until a new start condition occurs (read/write command followed by address cycles). 22.3.
SAM9G20 Figure 22-2: Parity Generation for 512/1024/2048/4096 8-bit Words 1st byte 2nd byte Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P8' 3rd byte Bit7 Bit7 Bit6 Bit6 Bit5 Bit5 Bit4 Bit4 Bit3 Bit3 Bit2 Bit2 Bit1 Bit1 Bit0 Bit0 P8 Bit7 Bit7 Bit6 Bit6 Bit5 Bit5 Bit4 Bit4 Bit3 Bit3 Bit2 Bit2 Bit1 Bit1 Bit0 Bit0 P8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 P8' P1 P1' P1
SAM9G20 Parity Generation for 512/1024/2048/4096 16-bit Words (Page size -3 )th word (Page size -2 )th word (Page size -1 )th word Page size th word 4th word 1st word 2nd word 3rd word (+) Figure 22-3: To calculate P8’ to PX’ and P8 to PX, apply the algorithm that follows. DS60001516A-page 212 2017 Microchip Technology Inc.
SAM9G20 Page size = 2n for i =0 to n begin for (j = 0 to page_size_word) begin if(j[i] ==1) P[2i+3]= bit15(+)bit14(+)bit13(+)bit12(+) bit11(+)bit10(+)bit9(+)bit8(+) bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2n+3] else P[2i+3]’=bit15(+)bit14(+)bit13(+)bit12(+) bit11(+)bit10(+)bit9(+)bit8(+) bit7(+)bit6(+)bit5(+)bit4(+)bit3(+) bit2(+)bit1(+)bit0(+)P[2i+3]' end end 2017 Microchip Technology Inc.
SAM9G20 22.
SAM9G20 22.4.1 ECC Control Register Name:ECC_CR Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RST RST: RESET Parity Provides reset to current ECC by software. 1: Reset ECC Parity registers 0: No effect 2017 Microchip Technology Inc.
SAM9G20 22.4.2 ECC Mode Register Name:ECC_MR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 4 3 – 2 – 1 TYPCORREC 0 PAGESIZE PAGESIZE: Page Size This field defines the page size of the NAND Flash device.
SAM9G20 22.4.3 ECC Status Register 1 Name:ECC_SR1 Access:Read-only 31 – 30 ECCERR7 29 ECCERR7 28 RECERR7 27 – 26 ECCERR6 25 ECCERR6 24 RECERR6 23 – 22 ECCERR5 21 ECCERR5 20 RECERR5 19 – 18 ECCERR4 17 ECCERR4 16 RECERR4 15 – 14 MULERR3 13 ECCERR3 12 RECERR3 11 – 10 MULERR2 9 ECCERR2 8 RECERR2 7 – 6 MULERR1 5 ECCERR1 4 RECERR1 3 – 2 ECCERR0 1 ECCERR0 0 RECERR0 RECERR0: Recoverable Error 0: No Errors Detected. 1: Errors Detected.
SAM9G20 ECCERR2: ECC Error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. Read ECC Parity 2 register, the error occurred at the location which contains a 1 in the least significant 24 bits. MULERR2: Multiple Error in the page between the 512th and the 767th bytes or the 1024th and the 1535th bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected.
SAM9G20 ECCERR5: ECC Error in the page between the 1280th and the 1535th bytes or the 2560th and the 3071st bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. Read ECC Parity 5 register, the error occurred at the location which contains a 1 in the least significant 24 bits. MULERR5: Multiple Error in the page between the 1280th and the 1535th bytes or the 2560th and the 3071st bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected.
SAM9G20 22.4.
SAM9G20 ECCERR10: ECC Error in the page between the 2560th and the 2815th bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. Read ECC Parity 10 register, the error occurred at the location which contains a 1 in the least significant 24 bits. MULERR10: Multiple Error in the page between the 2560th and the 2815th bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected.
SAM9G20 ECCERR13: ECC Error in the page between the 3328th and the 3583rd bytes Fixed to 0 if TYPECORREC = 0. 0: No Errors Detected. 1: A single bit error occurred in the ECC bytes. Read ECC Parity 13 register, the error occurred at the location which contains a 1 in the least significant 24 bits. MULERR13: Multiple Error in the page between the 3328th and the 3583rd bytes Fixed to 0 if TYPECORREC = 0. 0: No Multiple Errors Detected. 1: Multiple Errors Detected.
SAM9G20 22.5 Registers for 1 ECC for a page of 512/1024/2048/4096 bytes 22.5.1 ECC Parity Register 0 Name:ECC_PR0 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 WORDADDR 7 6 5 WORDADDR 4 BITADDR Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.5.2 ECC Parity Register 1 Name:ECC_PR1 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 NPARITY 7 6 5 4 NPARITY NPARITY Parity N DS60001516A-page 224 2017 Microchip Technology Inc.
SAM9G20 22.6 Registers for 1 ECC per 512 bytes for a page of 512/2048/4096 bytes, 8-bit word 22.6.1 ECC Parity Register 0 Name:ECC_PR0 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 NPARITY0 19 18 17 16 15 14 13 12 11 10 9 8 1 BITADDR0 0 NPARITY0 7 6 5 WORDADDR0 WORDADD0 4 3 2 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.6.2 ECC Parity Register 1 Name:ECC_PR1 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 NPARITY1 19 18 17 16 15 14 13 12 11 10 9 8 1 BITADDR1 0 NPARITY1 7 6 5 WORDADDR1 WORDADD1 4 3 2 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.6.3 ECC Parity Register 2 Name:ECC_PR2 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 NPARITY2 19 18 17 16 15 14 13 12 11 10 9 8 1 BITADDR2 0 NPARITY2 7 6 5 WORDADDR2 WORDADD2 4 3 2 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.6.4 ECC Parity Register 3 Name:ECC_PR3 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 NPARITY3 19 18 17 16 15 14 13 12 11 10 9 8 1 BITADDR3 0 NPARITY3 7 6 5 WORDADDR3 WORDADD3 4 3 2 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.6.5 ECC Parity Register 4 Name:ECC_PR4 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 NPARITY4 19 18 17 16 15 14 13 12 11 10 9 8 1 BITADDR4 0 NPARITY4 7 6 5 WORDADDR4 WORDADD4 4 3 2 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.6.6 ECC Parity Register 5 Name:ECC_PR5 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 NPARITY5 19 18 17 16 15 14 13 12 11 10 9 8 1 BITADDR5 0 NPARITY5 7 6 5 WORDADDR5 WORDADD5 4 3 2 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.6.7 ECC Parity Register 6 Name:ECC_PR6 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 NPARITY6 19 18 17 16 15 14 13 12 11 10 9 8 1 BITADDR6 0 NPARITY6 7 6 5 WORDADDR6 WORDADD6 4 3 2 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.6.8 ECC Parity Register 7 Name:ECC_PR7 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 NPARITY7 19 18 17 16 15 14 13 12 11 10 9 8 1 BITADDR7 0 NPARITY7 7 6 5 WORDADDR7 WORDADD7 4 3 2 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.7 Registers for 1 ECC per 256 bytes for a page of 512/2048/4096 bytes, 8-bit word 22.7.1 ECC Parity Register 0 Name:ECC_PR0 Access:Read-only 31 – 30 – 29 – 28 – 23 0 22 21 20 15 14 13 12 4 NPARITY0 7 6 5 WORDADDR0 27 – 26 – 25 – 24 – 18 17 16 11 0 10 9 WORDADD0 8 3 2 1 BITADDR0 0 19 NPARITY0 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.7.
SAM9G20 22.7.3 ECC Parity Register 2 Name:ECC_PR2 Access:Read-only 31 – 30 – 29 – 28 – 23 0 22 21 20 15 14 13 12 4 NPARITY2 7 6 5 WORDADDR2 27 – 26 – 25 – 24 – 18 17 16 11 0 10 9 WORDADD2 8 3 2 1 BITADDR2 0 19 NPARITY2 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.7.4 ECC Parity Register 3 Name:ECC_PR3 Access:Read-only 31 – 30 – 29 – 28 – 23 0 22 21 20 15 14 13 12 4 NPARITY3 7 6 5 WORDADDR3 27 – 26 – 25 – 24 – 18 17 16 11 0 10 9 WORDADD3 8 3 2 1 BITADDR3 0 19 NPARITY3 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.7.
SAM9G20 22.7.6 ECC Parity Register 5 Name:ECC_PR5 Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 0 22 21 20 19 NPARITY5 18 17 16 15 14 13 12 11 0 10 9 WORDADD5 8 4 3 2 1 BITADDR5 0 NPARITY5 7 6 5 WORDADDR5 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.7.7 ECC Parity Register 6 Name:ECC_PR6 Access:Read-only 31 – 30 – 29 – 28 – 23 0 22 21 20 15 14 13 12 4 NPARITY6 7 6 5 WORDADDR6 27 – 26 – 25 – 24 – 18 17 16 11 0 10 9 WORDADDR6 8 3 2 1 BITADDR6 0 19 NPARITY6 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.7.8 ECC Parity Register 7 Name:ECC_PR7 Access:Read-only 31 – 30 – 29 – 28 – 23 0 22 21 20 15 14 13 12 4 NPARITY7 7 6 5 WORDADDR7 27 – 26 – 25 – 24 – 18 17 16 11 0 10 9 WORDADDR7 8 3 2 1 BITADDR7 0 19 NPARITY7 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.7.9 ECC Parity Register 8 Name:ECC_PR8 Access:Read-only 31 – 30 – 29 – 28 – 23 0 22 21 20 15 14 13 12 4 NPARITY8 7 6 5 WORDADDR8 27 – 26 – 25 – 24 – 18 17 16 11 0 10 9 WORDADDR8 8 3 2 1 BITADDR8 0 19 NPARITY8 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.7.
SAM9G20 22.7.11 ECC Parity Register 10 Name:ECC_PR10 Access:Read-only 31 – 30 – 29 – 28 – 23 0 22 21 20 15 14 NPARITY10 13 12 7 6 4 5 WORDADDR10 27 – 26 – 25 – 24 – 18 17 16 11 0 10 9 WORDADDR10 8 3 2 1 BITADDR10 0 19 NPARITY10 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.7.12 ECC Parity Register 11 Name:ECC_PR11 Access:Read-only 31 – 30 – 29 – 28 – 23 0 22 21 20 15 14 NPARITY11 13 12 7 6 4 5 WORDADDR11 27 – 26 – 25 – 24 – 18 17 16 11 0 10 9 WORDADDR11 8 3 2 1 BITADDR11 0 19 NPARITY11 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.7.13 ECC Parity Register 12 Name:ECC_PR12 Access:Read-only 31 – 30 – 29 – 28 – 23 0 22 21 20 15 14 NPARITY12 13 12 7 6 4 5 WORDADDR12 27 – 26 – 25 – 24 – 18 17 16 11 0 10 9 WORDADDR12 8 3 2 1 BITADDR12 0 19 NPARITY12 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.7.14 ECC Parity Register 13 Name:ECC_PR13 Access:Read-only 31 – 30 – 29 – 28 – 23 0 22 21 20 15 14 NPARITY13 13 12 7 6 4 5 WORDADDR13 27 – 26 – 25 – 24 – 18 17 16 11 0 10 9 WORDADDR13 8 3 2 1 BITADDR13 0 19 NPARITY13 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.7.15 ECC Parity Register 14 Name:ECC_PR14 Access:Read-only 31 – 30 – 29 – 28 – 23 0 22 21 20 15 14 NPARITY14 13 12 7 6 4 5 WORDADDR14 27 – 26 – 25 – 24 – 18 17 16 11 0 10 9 WORDADDR14 8 3 2 1 BITADDR14 0 19 NPARITY14 Once the entire main area of a page is written with data, the register content must be stored at any free location of the spare area.
SAM9G20 22.7.
SAM9G20 23. Peripheral DMA Controller (PDC) 23.1 Overview The Peripheral DMA Controller (PDC) transfers data between on-chip serial peripherals and the on- and/or off-chip memories. The link between the PDC and a serial peripheral is operated by the AHB to ABP bridge. The PDC contains 24 channels. The full-duplex peripherals feature 21 mono directional channels used in pairs (transmit only or receive only). The half-duplex peripherals feature 1 bi-directional channel.
SAM9G20 23.2 Block Diagram Figure 23-1: Block Diagram FULL DUPLEX PERIPHERAL PDC THR PDC Channel A RHR PDC Channel B Control Status & Control HALF DUPLEX PERIPHERAL Control THR PDC Channel C RHR Control Status & Control RECEIVE or TRANSMIT PERIPHERAL RHR or THR Control 23.3 23.3.1 PDC Channel D Status & Control Functional Description Configuration The PDC channel user interface enables the user to configure and control data transfers for each channel.
SAM9G20 The PDC has dedicated status registers which indicate if the transfer is enabled or disabled for each channel. The status for each channel is located in the associated peripheral status register. Transfers can be enabled and/or disabled by setting TXTEN/TXTDIS and RXTEN/ RXTDIS in the peripheral’s Transfer Control Register. At the end of a transfer, the PDC channel sends status flags to its associated peripheral.
SAM9G20 23.3.5.3 Receive Buffer Full This flag is set when PERIPH_RCR reaches zero with PERIPH_RNCR also set to zero and the last data has been transferred to memory. It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR. 23.3.5.4 Transmit Buffer Empty This flag is set when PERIPH_TCR reaches zero with PERIPH_TNCR also set to zero and the last data has been written into peripheral THR. It is reset by writing a non zero value in PERIPH_TCR or PERIPH_TNCR.
SAM9G20 23.
SAM9G20 23.4.1 Receive Pointer Register Name:PERIPH_RPR Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXPTR 23 22 21 20 RXPTR 15 14 13 12 RXPTR 7 6 5 4 RXPTR RXPTR: Receive Pointer Register RXPTR must be set to receive buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR. DS60001516A-page 254 2017 Microchip Technology Inc.
SAM9G20 23.4.2 Receive Counter Register Name:PERIPH_RCR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXCTR 7 6 5 4 RXCTR RXCTR: Receive Counter Register RXCTR must be set to receive buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
SAM9G20 23.4.3 Transmit Pointer Register Name:PERIPH_TPR Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXPTR 23 22 21 20 TXPTR 15 14 13 12 TXPTR 7 6 5 4 TXPTR TXPTR: Transmit Counter Register TXPTR must be set to transmit buffer address. When a half duplex peripheral is connected to the PDC, RXPTR = TXPTR. DS60001516A-page 256 2017 Microchip Technology Inc.
SAM9G20 23.4.4 Transmit Counter Register Name:PERIPH_TCR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXCTR 7 6 5 4 TXCTR TXCTR: Transmit Counter Register TXCTR must be set to transmit buffer size. When a half duplex peripheral is connected to the PDC, RXCTR = TXCTR.
SAM9G20 23.4.5 Receive Next Pointer Register Name:PERIPH_RNPR Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RXNPTR 23 22 21 20 RXNPTR 15 14 13 12 RXNPTR 7 6 5 4 RXNPTR RXNPTR: Receive Next Pointer RXNPTR contains next receive buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR. DS60001516A-page 258 2017 Microchip Technology Inc.
SAM9G20 23.4.6 Receive Next Counter Register Name:PERIPH_RNCR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RXNCTR 7 6 5 4 RXNCTR RXNCTR: Receive Next Counter RXNCTR contains next receive buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR. 2017 Microchip Technology Inc.
SAM9G20 23.4.7 Transmit Next Pointer Register Name:PERIPH_TNPR Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TXNPTR 23 22 21 20 TXNPTR 15 14 13 12 TXNPTR 7 6 5 4 TXNPTR TXNPTR: Transmit Next Pointer TXNPTR contains next transmit buffer address. When a half duplex peripheral is connected to the PDC, RXNPTR = TXNPTR. DS60001516A-page 260 2017 Microchip Technology Inc.
SAM9G20 23.4.8 Transmit Next Counter Register Name:PERIPH_TNCR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TXNCTR 7 6 5 4 TXNCTR TXNCTR: Transmit Counter Next TXNCTR contains next transmit buffer size. When a half duplex peripheral is connected to the PDC, RXNCTR = TXNCTR. 2017 Microchip Technology Inc.
SAM9G20 23.4.9 Transfer Control Register Name:PERIPH_PTCR Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 TXTDIS 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXTDIS 0 RXTEN RXTEN: Receiver Transfer Enable 0: No effect. 1: Enables PDC receiver channel requests if RXTDIS is not set.
SAM9G20 23.4.10 Transfer Status Register Name:PERIPH_PTSR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 TXTEN 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 RXTEN RXTEN: Receiver Transfer Enable 0: PDC Receiver channel requests are disabled. 1: PDC Receiver channel requests are enabled. TXTEN: Transmitter Transfer Enable 0: PDC Transmitter channel requests are disabled.
SAM9G20 24. Clock Generator 24.1 Overview The Clock Generator is made up of 2 PLLs, a Main Oscillator, as well as an RC Oscillator and a 32768 Hz low-power Oscillator. It provides the following clocks: • SLCK, the Slow Clock, which is the only permanent clock within the system • MAINCK is the output of the Main Oscillator The Clock Generator User Interface is embedded within the Power Management Controller one and is described in Section 25.9 “Power Management Controller (PMC) User Interface”.
SAM9G20 24.4.1 Main Oscillator Connections The Clock Generator integrates a Main Oscillator that is designed for a 3 to 20 MHz fundamental crystal. The typical crystal connection is illustrated in Figure 24-3. For further details on the electrical characteristics of the Main Oscillator, see Section 40.2 “DC Characteristics”. Figure 24-3: Typical Crystal Connection AT91 Microcontroller XIN XOUT GND 1K 24.4.
SAM9G20 24.5 Divider and PLL Block The PLL embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must respect the PLL minimum input frequency when programming the divider. Figure 24-4 shows the block diagram of the divider and PLL block. Figure 24-4: Divider and PLL Block Diagram DIVB Divider B MAINCK DIVA Divider A MULB OUTB PLL B MULA PLLBCK OUTA PLL A PLLACK PLLBCOUNT PLL B Counter LOCKB PLLACOUNT SLCK 24.5.
SAM9G20 25. Power Management Controller (PMC) 25.1 Overview The Power Management Controller (PMC) optimizes power consumption by controlling all system and user peripheral clocks. The PMC enables/disables the clock inputs to many of the peripherals and the Arm Processor. The Power Management Controller provides the following clocks: • MCK, the Master Clock, programmable from a few hundred Hz to the maximum operating frequency of the device.
SAM9G20 Note: The Arm Wait for Interrupt mode is entered by a CP15 coprocessor operation. Refer to the Microchip application note, Optimizing Power Consumption of AT91SAM9261-based Systems, lit. number 6217. When the Processor Clock is disabled, the current instruction is finished before the clock is stopped, but this does not prevent data transfers from other masters of the system bus. 25.4 USB Clock Controller The USB Source Clock is always generated from the PLL B output.
SAM9G20 25.7 1. Programming Sequence Enabling the Main Oscillator: The main oscillator is enabled by setting the MOSCEN field in the CKGR_MOR. In some cases it may be advantageous to define a start-up time. This can be achieved by writing a value in the OSCOUNT field in the CKGR_MOR. Once this register has been correctly configured, the user must wait for MOSCS field in the PMC_SR to be set.
SAM9G20 Once the PMC_PLLB register has been written, the user must wait for the LOCKB bit to be set in the PMC_SR. This can be done either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to LOCKB has been enabled in the PMC_IER. All parameters in CKGR_PLLBR can be programmed in a single write operation. If at some stage one of the following parameters, MULB, DIVB is modified, LOCKB bit will go low to indicate that PLL B is not ready yet.
SAM9G20 wait (MCKRDY=1) The Master Clock is main clock divided by 16. The Processor Clock is the Master Clock. 6. Selection of Programmable clocks Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR. Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR registers. Depending on the system used, 2 Programmable clocks can be enabled or disabled. The PMC_SCSR provides a clear indication as to which Programmable clock is enabled.
SAM9G20 25.8 25.8.1 Clock Switching Details Master Clock Switching Timings Table 25-1and Table 25-2 give the worst case timings required for the Master Clock to switch from one selected clock to another one. This is in the event that the prescaler is de-activated. When the prescaler is activated, an additional time of 64 clock cycles of the new selected clock has to be added. Table 25-1: Clock Switching Timings (Worst Case) From Main Clock SLCK PLL Clock – 4 x SLCK + 2.5 x Main Clock 0.
SAM9G20 25.8.2 Clock Switching Waveforms Figure 25-3: Switch Master Clock from Slow Clock to PLL Clock Slow Clock PLL Clock LOCK MCKRDY Master Clock Write PMC_MCKR Figure 25-4: Switch Master Clock from Main Clock to Slow Clock Slow Clock Main Clock MCKRDY Master Clock Write PMC_MCKR 2017 Microchip Technology Inc.
SAM9G20 Figure 25-5: Change PLLA Programming Slow Clock PLLA Clock LOCK MCKRDY Master Clock Slow Clock Write CKGR_PLLAR Figure 25-6: Change PLLB Programming Main Clock PLLB Clock LOCK MCKRDY Master Clock Main Clock Write CKGR_PLLBR DS60001516A-page 274 2017 Microchip Technology Inc.
SAM9G20 Figure 25-7: Programmable Clock Output Programming PLL Clock PCKRDY PCKx Output Write PMC_PCKx Write PMC_SCER Write PMC_SCDR 2017 Microchip Technology Inc.
SAM9G20 25.
SAM9G20 25.9.1 PMC System Clock Enable Register Name:PMC_SCER Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – PCK1 PCK0 7 6 5 4 3 2 1 0 UDP UHP – – – – – – UHP: USB Host Port Clock Enable 0: No effect. 1: Enables the 12 and 48 MHz clock of the USB Host Port. UDP: USB Device Port Clock Enable 0: No effect. 1: Enables the 48 MHz clock of the USB Device Port.
SAM9G20 25.9.2 PMC System Clock Disable Register Name:PMC_SCDR Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – PCK1 PCK0 7 6 5 4 3 2 1 0 UDP UHP – – – – – PCK PCK: Processor Clock Disable 0: No effect. 1: Disables the Processor clock. This is used to enter the processor in Idle Mode. UHP: USB Host Port Clock Disable 0: No effect.
SAM9G20 25.9.3 PMC System Clock Status Register Name:PMC_SCSR Access:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – PCK1 PCK0 7 6 5 4 3 2 1 0 UDP UHP – – – – – PCK PCK: Processor Clock Status 0: The Processor clock is disabled. 1: The Processor clock is enabled. UHP: USB Host Port Clock Status 0: The 12 and 48 MHz clock (UHPCK) of the USB Host Port is disabled.
SAM9G20 25.9.4 PMC Peripheral Clock Enable Register Name:PMC_PCER Access:Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 – – PIDx: Peripheral Clock x Enable 0: No effect. 1: Enables the corresponding peripheral clock.
SAM9G20 25.9.5 PMC Peripheral Clock Disable Register Name:PMC_PCDR Access:Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 – – PIDx: Peripheral Clock x Disable 0: No effect. 1: Disables the corresponding peripheral clock.
SAM9G20 25.9.6 PMC Peripheral Clock Status Register Name:PMC_PCSR Access:Read-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 – – PIDx: Peripheral Clock x Status 0: The corresponding peripheral clock is disabled.
SAM9G20 25.9.7 PMC Clock Generator Main Oscillator Register Name:CKGR_MOR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 – 2 – 1 OSCBYPASS 0 MOSCEN OSCOUNT 7 – 6 – 5 – 4 – MOSCEN: Main Oscillator Enable A crystal must be connected between XIN and XOUT. 0: The Main Oscillator is disabled. 1: The Main Oscillator is enabled. OSCBYPASS must be set to 0.
SAM9G20 25.9.8 PMC Clock Generator Main Clock Frequency Register Name:CKGR_MCFR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 MAINRDY 15 14 13 12 11 10 9 8 3 2 1 0 MAINF 7 6 5 4 MAINF MAINF: Main Clock Frequency Gives the number of Main Clock cycles within 16 Slow Clock periods. MAINRDY: Main Clock Ready 0: MAINF value is not valid or the Main Oscillator is disabled.
SAM9G20 25.9.9 PMC Clock Generator PLL A Register Name:CKGR_PLLAR Access:Read/Write 31 – 30 – 29 1 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 10 9 8 2 1 0 MULA 15 14 13 12 11 OUTA 7 PLLACOUNT 6 5 4 3 DIVA Possible limitations on PLL A input frequencies and multiplier factors should be checked before using the PMC. Warning: Bit 29 must always be set to 1 when programming the CKGR_PLLAR.
SAM9G20 25.9.10 PMC Clock Generator PLL B Register Name:CKGR_PLLBR Access:Read/Write 31 – 30 – 29 23 – 22 – 21 14 13 15 28 27 – 20 19 USBDIV 25 – 24 – 18 17 16 10 9 8 2 1 0 MULB 12 11 OUTB 7 26 – PLLBCOUNT 6 5 4 3 DIVB Possible limitations on PLL B input frequencies and multiplier factors should be checked before using the PMC.
SAM9G20 25.9.
SAM9G20 PDIV: Processor Clock Division PDIV Processor Clock Division 0 Processor Clock is Prescaler Output Clock divided by 1. 1 Processor Clock is Prescaler Output Clock divided by 2. Warning: If MDIV is written to 0, the write in PDIV is not taken in account and PDIV is forced to 0 (The Master Clock frequency cannot be superior to the Processor Clock frequency). DS60001516A-page 288 2017 Microchip Technology Inc.
SAM9G20 25.9.
SAM9G20 25.9.
SAM9G20 25.9.
SAM9G20 25.9.15 PMC Status Register Name:PMC_SR Access:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – PCKRDY1 PCKRDY0 7 6 5 4 3 2 1 0 OSC_SEL – – – MCKRDY LOCKB LOCKA MOSCS MOSCS: Main Oscillator Status 0: Main oscillator is not stabilized. 1: Main oscillator is stabilized. LOCKA: PLL A Lock Status 0: PLL A is not locked 1: PLL A is locked.
SAM9G20 25.9.
SAM9G20 25.9.17 PLL Charge Pump Current Register Name:PMC_PLLICPR Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – ICPLLB 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – ICPLLA ICPLLA: Charge Pump Current To optimize clock performance, this field must be programmed as specified in Section 40.5.7 “PLL Characteristics”. ICPLLB: Charge Pump Current Must be set to 0.
SAM9G20 26. Advanced Interrupt Controller (AIC) 26.1 Overview The Advanced Interrupt Controller (AIC) is an 8-level priority, individually maskable, vectored interrupt controller, providing handling of up to thirty-two interrupt sources. It is designed to substantially reduce the software and real-time overhead in handling internal and external interrupts. The AIC drives the nFIQ (fast interrupt request) and the nIRQ (standard interrupt request) inputs of an Arm processor.
SAM9G20 26.4 AIC Detailed Block Diagram Figure 26-3: AIC Detailed Block Diagram Advanced Interrupt Controller FIQ PIO Controller Fast Interrupt Controller External Source Input Stage Arm Processor nFIQ nIRQ IRQ0-IRQn Embedded Peripherals Interrupt Priority Controller Fast Forcing PIOIRQ Internal Source Input Stage Processor Clock Power Management Controller User Interface Wake Up APB 26.
SAM9G20 The peripheral identification defined at the product level corresponds to the interrupt source number (as well as the bit number controlling the clock of the peripheral). Consequently, to simplify the description of the functional operations and the user interface, the interrupt sources are named FIQ, SYS, and PID2 to PID31. 26.7 26.7.1 26.7.1.1 Functional Description Interrupt Source Control Interrupt Source Mode The Advanced Interrupt Controller independently programs each interrupt source.
SAM9G20 26.7.1.5 Internal Interrupt Source Input Stage Figure 26-4: Internal Interrupt Source Input Stage AIC_SMRI (SRCTYPE) Level/ Edge Source i AIC_IPR AIC_IMR Fast Interrupt Controller or Priority Controller Edge AIC_IECR Detector Set Clear FF AIC_ISCR AIC_ICCR AIC_IDCR 26.7.1.
SAM9G20 26.7.2.1 External Interrupt Edge Triggered Source Figure 26-6: External Interrupt Edge Triggered Source MCK IRQ or FIQ (Positive Edge) IRQ or FIQ (Negative Edge) nIRQ Maximum IRQ Latency = 4 Cycles nFIQ Maximum FIQ Latency = 4 Cycles 26.7.2.2 External Interrupt Level Sensitive Source Figure 26-7: External Interrupt Level Sensitive Source MCK IRQ or FIQ (High Level) IRQ or FIQ (Low Level) nIRQ Maximum IRQ Latency = 3 Cycles nFIQ Maximum FIQ Latency = 3 cycles 26.7.2.
SAM9G20 26.7.2.4 Internal Interrupt Level Sensitive Source Figure 26-9: Internal Interrupt Level Sensitive Source MCK nIRQ Maximum IRQ Latency = 3.5 Cycles Peripheral Interrupt Becomes Active 26.7.3 26.7.3.1 Normal Interrupt Priority Controller An 8-level priority controller drives the nIRQ line of the processor, depending on the interrupt conditions occurring on the interrupt sources 1 to 31 (except for those programmed in Fast Forcing).
SAM9G20 This feature is often not used when the application is based on an operating system (either real time or not). Operating systems often have a single entry point for all the interrupts and the first task performed is to discern the source of the interrupt. However, it is strongly recommended to port the operating system on AT91 products by supporting the interrupt vectoring.
SAM9G20 26.7.4 26.7.4.1 Fast Interrupt Fast Interrupt Source The interrupt source 0 is the only source which can raise a fast interrupt request to the processor except if fast forcing is used. The interrupt source 0 is generally connected to a FIQ pin of the product, either directly or through a PIO Controller. 26.7.4.2 Fast Interrupt Control The fast interrupt logic of the AIC has no priority controller.
SAM9G20 26.7.4.5 Fast Forcing The Fast Forcing feature of the advanced interrupt controller provides redirection of any normal Interrupt source on the fast interrupt controller. Fast Forcing is enabled or disabled by writing to the Fast Forcing Enable Register (AIC_FFER) and the Fast Forcing Disable Register (AIC_FFDR). Writing to these registers results in an update of the Fast Forcing Status Register (AIC_FFSR) that controls the feature for each internal or external interrupt source.
SAM9G20 When the Protect Mode is enabled, the AIC performs interrupt stacking only when a write access is performed on the AIC_IVR. Therefore, the Interrupt Service Routines must write (arbitrary data) to the AIC_IVR just after reading it. The new context of the AIC, including the value of the Interrupt Status Register (AIC_ISR), is updated with the current interrupt only when AIC_IVR is written. An AIC_IVR read on its own (e.g., by a debugger), modifies neither the AIC context nor the AIC_ISR.
SAM9G20 26.8 Advanced Interrupt Controller (AIC) User Interface The AIC is mapped at the address 0xFFFF F000. It has a total 4-Kbyte addressing space. This permits the vectoring feature, as the PCrelative load/store instructions of the Arm processor support only a ± 4-Kbyte offset.
SAM9G20 26.8.1 AIC Source Mode Register Name:AIC_SMR0..AIC_SMR31 Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 4 3 2 1 0 – – – 5 SRCTYPE PRIOR PRIOR: Priority Level Programs the priority level for all sources except FIQ source (source 0). The priority level can be between 0 (lowest) and 7 (highest).
SAM9G20 26.8.2 AIC Source Vector Register Name:AIC_SVR0..AIC_SVR31 Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 VECTOR 23 22 21 20 VECTOR 15 14 13 12 VECTOR 7 6 5 4 VECTOR VECTOR: Source Vector The user may store in these registers the addresses of the corresponding handler for each interrupt source. 2017 Microchip Technology Inc.
SAM9G20 26.8.3 AIC Interrupt Vector Register Name: AIC_IVR Access:Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IRQV 23 22 21 20 IRQV 15 14 13 12 IRQV 7 6 5 4 IRQV IRQV: Interrupt Vector Register The Interrupt Vector Register contains the vector programmed by the user in the Source Vector Register corresponding to the current interrupt. The Source Vector Register is indexed using the current interrupt number when the Interrupt Vector Register is read.
SAM9G20 26.8.4 AIC FIQ Vector Register Name: AIC_FVR Access:Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 FIQV 23 22 21 20 FIQV 15 14 13 12 FIQV 7 6 5 4 FIQV FIQV: FIQ Vector Register The FIQ Vector Register contains the vector programmed by the user in the Source Vector Register 0. When there is no fast interrupt, the FIQ Vector Register reads the value stored in AIC_SPU. 2017 Microchip Technology Inc.
SAM9G20 26.8.5 AIC Interrupt Status Register Name: AIC_ISR Access:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 4 3 2 1 0 7 6 5 – – – IRQID IRQID: Current Interrupt Identifier The Interrupt Status Register returns the current interrupt source number. DS60001516A-page 310 2017 Microchip Technology Inc.
SAM9G20 26.8.6 AIC Interrupt Pending Register Name: AIC_IPR Access:Read-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ FIQ, SYS, PID2–PID31: Interrupt Pending 0: Corresponding interrupt is not pending.
SAM9G20 26.8.7 AIC Interrupt Mask Register Name:AIC_IMR Access:Read-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ FIQ, SYS, PID2–PID31: Interrupt Mask 0: Corresponding interrupt is disabled.
SAM9G20 26.8.8 AIC Core Interrupt Status Register Name: AIC_CISR Access:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – NIRQ NFIQ NFIQ: NFIQ Status 0: nFIQ line is deactivated. 1: nFIQ line is active. NIRQ: NIRQ Status 0: nIRQ line is deactivated. 1: nIRQ line is active. 2017 Microchip Technology Inc.
SAM9G20 26.8.9 AIC Interrupt Enable Command Register Name: AIC_IECR Access:Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ FIQ, SYS, PID2–PID31: Interrupt Enable 0: No effect. 1: Enables corresponding interrupt.
SAM9G20 26.8.10 AIC Interrupt Disable Command Register Name: AIC_IDCR Access:Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ FIQ, SYS, PID2–PID31: Interrupt Disable 0: No effect. 1: Disables corresponding interrupt.
SAM9G20 26.8.11 AIC Interrupt Clear Command Register Name:AIC_ICCR Access:Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ FIQ, SYS, PID2–PID31: Interrupt Clear 0: No effect. 1: Clears corresponding interrupt.
SAM9G20 26.8.12 AIC Interrupt Set Command Register Name: AIC_ISCR Access:Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS FIQ FIQ, SYS, PID2–PID31: Interrupt Set 0: No effect. 1: Sets corresponding interrupt.
SAM9G20 26.8.13 AIC End of Interrupt Command Register Name:AIC_EOICR Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – – The End of Interrupt Command Register is used by the interrupt routine to indicate that the interrupt treatment is complete.
SAM9G20 26.8.14 AIC Spurious Interrupt Vector Register Name:AIC_SPU Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SIVR 23 22 21 20 SIVR 15 14 13 12 SIVR 7 6 5 4 SIVR SIVR: Spurious Interrupt Vector Register The user may store the address of a spurious interrupt handler in this register. The written value is returned in AIC_IVR in case of a spurious interrupt and in AIC_FVR in case of a spurious fast interrupt. 2017 Microchip Technology Inc.
SAM9G20 26.8.15 AIC Debug Control Register Name:AIC_DCR Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – GMSK PROT PROT: Protection Mode 0: The Protection Mode is disabled. 1: The Protection Mode is enabled. GMSK: General Mask 0: The nIRQ and nFIQ lines are normally controlled by the AIC.
SAM9G20 26.8.16 AIC Fast Forcing Enable Register Name:AIC_FFER Access:Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – SYS, PID2–PID31: Fast Forcing Enable 0: No effect.
SAM9G20 26.8.17 AIC Fast Forcing Disable Register Name:AIC_FFDR Access:Write-only 31 30 29 28 27 26 25 24 PID31 PID30 PID29 PID28 PID27 PID26 PID25 PID24 23 22 21 20 19 18 17 16 PID23 PID22 PID21 PID20 PID19 PID18 PID17 PID16 15 14 13 12 11 10 9 8 PID15 PID14 PID13 PID12 PID11 PID10 PID9 PID8 7 6 5 4 3 2 1 0 PID7 PID6 PID5 PID4 PID3 PID2 SYS – SYS, PID2–PID31: Fast Forcing Disable 0: No effect.
SAM9G20 26.8.
SAM9G20 27. Debug Unit (DBGU) 27.1 Overview The Debug Unit provides a single entry point from the processor for access to all the debug capabilities of Microchip’s Arm-based systems. The Debug Unit features a two-pin UART that can be used for several debug and trace purposes and offers an ideal medium for in-situ programming solutions and debug monitor communications. The Debug Unit two-pin UART can be used stand-alone for general purpose serial communication.
SAM9G20 Table 27-1: Debug Unit Pin Description Pin Name Description Type DRXD Debug Receive Data Input DTXD Debug Transmit Data Output Figure 27-2: Debug Unit Application Example Boot Program Debug Monitor Trace Manager Debug Unit RS232 Drivers Programming Tool 27.3 27.3.1 Debug Console Trace Console Product Dependencies I/O Lines Depending on product integration, the Debug Unit pins may be multiplexed with PIO lines.
SAM9G20 Figure 27-3: Baud Rate Generator CD CD MCK 16-bit Counter OUT >1 1 0 Divide by 16 Baud Rate Clock 0 Receiver Sampling Clock 27.4.2 27.4.2.1 Receiver Receiver Reset, Enable and Disable After device reset, the Debug Unit receiver is disabled and must be enabled before being used. The receiver can be enabled by writing the control register DBGU_CR with the bit RXEN at 1. At this command, the receiver starts looking for a start bit.
SAM9G20 Figure 27-5: Character Reception Example: 8-bit, parity enabled 1 stop 0.5 bit period 1 bit period DRXD Sampling 27.4.2.3 D0 D1 True Start Detection D2 D3 D4 D5 D6 Stop Bit D7 Parity Bit Receiver Ready When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR (Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read.
SAM9G20 27.4.2.6 Receiver Framing Error When a start bit is detected, it generates a character reception when all the data bits have been sampled. The stop bit is also sampled and when it is detected at 0, the FRAME (Framing Error) bit in DBGU_SR is set at the same time the RXRDY bit is set. The bit FRAME remains high until the control register DBGU_CR is written with the bit RSTSTA at 1.
SAM9G20 Figure 27-11: Transmitter Control DBGU_THR Data 0 Data 1 Shift Register DTXD Data 0 Data 0 S Data 1 P stop S Data 1 P stop TXRDY TXEMPTY Write Data 0 in DBGU_THR 27.4.4 Write Data 1 in DBGU_THR Peripheral Data Controller Both the receiver and the transmitter of the Debug Unit's UART are generally connected to a Peripheral Data Controller (PDC) channel.
SAM9G20 Figure 27-12: Test Modes Automatic Echo RXD Receiver Transmitter Disabled TXD Local Loopback Disabled Receiver RXD VDD Disabled Transmitter Remote Loopback Receiver Transmitter 27.4.6 TXD VDD Disabled Disabled RXD TXD Debug Communication Channel Support The Debug Unit handles the signals COMMRX and COMMTX that come from the Debug Communication Channel of the Arm Processor and are driven by the In-circuit Emulator.
SAM9G20 27.4.7 Chip Identifier The Debug Unit features two chip identifier registers, DBGU_CIDR (Chip ID Register) and DBGU_EXID (Extension ID). Both registers contain a hard-wired value that is read-only.
SAM9G20 27.
SAM9G20 27.5.1 Debug Unit Control Register Name:DBGU_CR Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – RSTSTA 7 6 5 4 3 2 1 0 TXDIS TXEN RXDIS RXEN RSTTX RSTRX – – RSTRX: Reset Receiver 0: No effect. 1: The receiver logic is reset and disabled. If a character is being received, the reception is aborted. RSTTX: Reset Transmitter 0: No effect.
SAM9G20 27.5.
SAM9G20 27.5.
SAM9G20 27.5.
SAM9G20 27.5.
SAM9G20 27.5.6 Debug Unit Status Register Name:DBGU_SR Access:Read-only 31 30 29 28 27 26 25 24 COMMRX COMMTX – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – RXBUFF TXBUFE – TXEMPTY – 7 6 5 4 3 2 1 0 PARE FRAME OVRE ENDTX ENDRX – TXRDY RXRDY RXRDY: Receiver Ready 0: No character has been received since the last read of the DBGU_RHR or the receiver is disabled.
SAM9G20 RXBUFF: Receive Buffer Full 0: The buffer full signal from the receiver PDC channel is inactive. 1: The buffer full signal from the receiver PDC channel is active. COMMTX: Debug Communication Channel Write Status 0: COMMTX from the Arm processor is inactive. 1: COMMTX from the Arm processor is active. COMMRX: Debug Communication Channel Read Status 0: COMMRX from the Arm processor is inactive. 1: COMMRX from the Arm processor is active. 2017 Microchip Technology Inc.
SAM9G20 27.5.7 Debug Unit Receiver Holding Register Name:DBGU_RHR Access:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 RXCHR RXCHR: Received Character Last received character if RXRDY is set. DS60001516A-page 340 2017 Microchip Technology Inc.
SAM9G20 27.5.8 Debug Unit Transmit Holding Register Name:DBGU_THR Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 TXCHR TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. 2017 Microchip Technology Inc.
SAM9G20 27.5.9 Debug Unit Baud Rate Generator Register Name:DBGU_BRGR Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD CD: Clock Divisor CD Baud Rate Clock 0 Disabled 1 MCK 2–65535 DS60001516A-page 342 MCK / (CD x 16) 2017 Microchip Technology Inc.
SAM9G20 27.5.10 Debug Unit Chip ID Register Name:DBGU_CIDR Access:Read-only 31 30 29 EXT 23 28 27 26 NVPTYP 22 21 20 19 18 ARCH 15 14 13 6 24 17 16 9 8 1 0 SRAMSIZ 12 11 10 NVPSIZ2 7 25 ARCH NVPSIZ 5 4 3 EPROC 2 VERSION VERSION: Version of the Device Current version of the device.
SAM9G20 NVPSIZ2 Second Nonvolatile Program Memory Size NVPSIZ2 Size 0 0 0 0 None 0 0 0 1 8K bytes 0 0 1 0 16K bytes 0 0 1 1 32K bytes 0 1 0 0 Reserved 0 1 0 1 64K bytes 0 1 1 0 Reserved 0 1 1 1 128K bytes 1 0 0 0 Reserved 1 0 0 1 256K bytes 1 0 1 0 512K bytes 1 0 1 1 Reserved 1 1 0 0 1024K bytes 1 1 0 1 Reserved 1 1 1 0 2048K bytes 1 1 1 1 Reserved SRAMSIZ: Internal SRAM Size SRAMSIZ Size 0 0 0 0 Reserved 0 0 0 1 1K
SAM9G20 ARCH: Architecture Identifier ARCH Hex Bin Architecture 0x19 0001 1001 AT91SAM9xx Series 0x29 0010 1001 AT91SAM9XExx Series 0x34 0011 0100 AT91x34 Series 0x37 0011 0111 CAP7 Series 0x39 0011 1001 CAP9 Series 0x3B 0011 1011 CAP11 Series 0x40 0100 0000 AT91x40 Series 0x42 0100 0010 AT91x42 Series 0x55 0101 0101 AT91x55 Series 0x60 0110 0000 AT91SAM7Axx Series 0x61 0110 0001 AT91SAM7AQxx Series 0x63 0110 0011 AT91x63 Series 0x70 0111 0000 AT91SAM7Sxx Series 0x7
SAM9G20 27.5.11 Debug Unit Chip ID Extension Register Name:DBGU_EXID Access:Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 EXID 23 22 21 20 EXID 15 14 13 12 EXID 7 6 5 4 EXID EXID: Chip ID Extension Reads 0 if the bit EXT in DBGU_CIDR is 0. DS60001516A-page 346 2017 Microchip Technology Inc.
SAM9G20 27.5.12 Debug Unit Force NTRST Register Name: DBGU_FNR Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – FNTRST FNTRST: Force NTRST 0: NTRST of the Arm processor’s TAP controller is driven by the power_on_reset signal. 1: NTRST of the Arm processor’s TAP controller is held low. 2017 Microchip Technology Inc.
SAM9G20 28. Parallel Input Output Controller (PIO) 28.1 Overview The Parallel Input/Output Controller (PIO) manages up to 32 fully programmable input/output lines. Each I/O line may be dedicated as a general-purpose I/O or be assigned to a function of an embedded peripheral. This assures effective optimization of the pins of a product. Each I/O line is associated with a bit number in all of the 32-bit registers of the 32-bit wide User Interface.
SAM9G20 Figure 28-2: Application Block Diagram On-Chip Peripheral Drivers Keyboard Driver Control & Command Driver On-Chip Peripherals PIO Controller Keyboard Driver 28.3 28.3.1 General Purpose I/Os External Devices Product Dependencies Pin Multiplexing Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os.
SAM9G20 28.4 Functional Description The PIO Controller features up to 32 fully-programmable I/O lines. Most of the control logic associated to each I/O is represented in Figure 28-3. In this description each signal shown represents but one of up to 32 possible indexes.
SAM9G20 28.4.1 Pull-up Resistor Control Each I/O line is designed with an embedded pull-up resistor. The pull-up resistor can be enabled or disabled by writing respectively PIO_PUER (Pull-up Enable Register) and PIO_PUDR (Pull-up Disable Resistor). Writing in these registers results in setting or clearing the corresponding bit in PIO_PUSR (Pull-up Status Register). Reading a 1 in PIO_PUSR means the pull-up is disabled and reading a 0 means the pull-up is enabled.
SAM9G20 28.4.6 Multi Drive Control (Open Drain) Each I/O can be independently programmed in Open Drain by using the Multi Drive feature. This feature permits several drivers to be connected on the I/O line which is driven low only by each device. An external pull-up resistor (or enabling of the internal one) is generally required to guarantee a high level on the line. The Multi Drive feature is controlled by PIO_MDER (Multi-driver Enable Register) and PIO_MDDR (Multi-driver Disable Register).
SAM9G20 Figure 28-5: Input Glitch Filter Timing MCK up to 1.5 cycles Pin Level 1 cycle 1 cycle 1 cycle 1 cycle PIO_PDSR if PIO_IFSR = 0 2 cycles up to 2.5 cycles PIO_PDSR if PIO_IFSR = 1 28.4.10 1 cycle up to 2 cycles Input Change Interrupt The PIO Controller can be programmed to generate an interrupt when it detects an input change on an I/O line.
SAM9G20 • I/O lines 16 to 19 assigned to peripheral A functions with pull-up resistor • I/O lines 20 to 23 assigned to peripheral B functions, no pull-up resistor • I/O line 24 to 27 assigned to peripheral A with Input Change Interrupt and pull-up resistor Table 28-1: Programming Example Register Value to be Written PIO_PER 0x0000 FFFF PIO_PDR 0x0FFF 0000 PIO_OER 0x0000 00FF PIO_ODR 0x0FFF FF00 PIO_IFER 0x0000 0F00 PIO_IFDR 0x0FFF F0FF PIO_SODR 0x0000 0000 PIO_CODR 0x0FFF FFFF PIO_IER 0
SAM9G20 28.6 Parallel Input/Output Controller (PIO) User Interface Each I/O line controlled by the PIO Controller is associated with a bit in each of the PIO Controller User Interface registers. Each register is 32 bits wide. If a parallel I/O line is not defined, writing to the corresponding bits has no effect. Undefined bits read zero. If the I/O line is not multiplexed with any peripheral, the I/O line is controlled by the PIO Controller and PIO_PSR returns 1 systematically.
SAM9G20 Table 28-2: Register Mapping (Continued) Offset Register 0x007C to 0x009C Reserved 0x00A0 Output Write Enable 0x00A4 Name Access Reset PIO_OWER Write-only – Output Write Disable PIO_OWDR Write-only – 0x00A8 Output Write Status Register PIO_OWSR Read-only 0x00000000 0x00AC Reserved Note 1: Reset value of PIO_PSR depends on the product implementation. 2: PIO_ODSR is Read-only or Read/Write depending on PIO_OWSR I/O lines.
SAM9G20 28.6.1 PIO Controller PIO Enable Register Name:PIO_PER Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: PIO Enable 0: No effect. 1: Enables the PIO to control the corresponding pin (disables peripheral control of the pin). 2017 Microchip Technology Inc.
SAM9G20 28.6.2 PIO Controller PIO Disable Register Name:PIO_PDR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: PIO Disable 0: No effect. 1: Disables the PIO from controlling the corresponding pin (enables peripheral control of the pin).
SAM9G20 28.6.3 PIO Controller PIO Status Register Name:PIO_PSR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: PIO Status 0: PIO is inactive on the corresponding I/O line (peripheral is active).
SAM9G20 28.6.4 PIO Controller Output Enable Register Name:PIO_OER Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Output Enable 0: No effect. 1: Enables the output on the I/O line. DS60001516A-page 360 2017 Microchip Technology Inc.
SAM9G20 28.6.5 PIO Controller Output Disable Register Name:PIO_ODR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Output Disable 0: No effect. 1: Disables the output on the I/O line. 2017 Microchip Technology Inc.
SAM9G20 28.6.6 PIO Controller Output Status Register Name:PIO_OSR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Output Status 0: The I/O line is a pure input. 1: The I/O line is enabled in output. DS60001516A-page 362 2017 Microchip Technology Inc.
SAM9G20 28.6.7 PIO Controller Input Filter Enable Register Name:PIO_IFER Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Input Filter Enable 0: No effect. 1: Enables the input glitch filter on the I/O line. 2017 Microchip Technology Inc.
SAM9G20 28.6.8 PIO Controller Input Filter Disable Register Name:PIO_IFDR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Input Filter Disable 0: No effect. 1: Disables the input glitch filter on the I/O line.
SAM9G20 28.6.9 PIO Controller Input Filter Status Register Name:PIO_IFSR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Input Filer Status 0: The input glitch filter is disabled on the I/O line. 1: The input glitch filter is enabled on the I/O line.
SAM9G20 28.6.10 PIO Controller Set Output Data Register Name:PIO_SODR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Set Output Data 0: No effect. 1: Sets the data to be driven on the I/O line. DS60001516A-page 366 2017 Microchip Technology Inc.
SAM9G20 28.6.11 PIO Controller Clear Output Data Register Name:PIO_CODR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Set Output Data 0: No effect. 1: Clears the data to be driven on the I/O line. 2017 Microchip Technology Inc.
SAM9G20 28.6.12 PIO Controller Output Data Status Register Name:PIO_ODSR Access:Read-only or Read/Write 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Output Data Status 0: The data to be driven on the I/O line is 0. 1: The data to be driven on the I/O line is 1.
SAM9G20 28.6.13 PIO Controller Pin Data Status Register Name:PIO_PDSR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Output Data Status 0: The I/O line is at level 0. 1: The I/O line is at level 1. 2017 Microchip Technology Inc.
SAM9G20 28.6.14 PIO Controller Interrupt Enable Register Name:PIO_IER Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Input Change Interrupt Enable 0: No effect. 1: Enables the Input Change Interrupt on the I/O line.
SAM9G20 28.6.15 PIO Controller Interrupt Disable Register Name:PIO_IDR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Input Change Interrupt Disable 0: No effect. 1: Disables the Input Change Interrupt on the I/O line. 2017 Microchip Technology Inc.
SAM9G20 28.6.16 PIO Controller Interrupt Mask Register Name:PIO_IMR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Input Change Interrupt Mask 0: Input Change Interrupt is disabled on the I/O line. 1: Input Change Interrupt is enabled on the I/O line.
SAM9G20 28.6.17 PIO Controller Interrupt Status Register Name:PIO_ISR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Input Change Interrupt Status 0: No Input Change has been detected on the I/O line since PIO_ISR was last read or since reset.
SAM9G20 28.6.18 PIO Multi-driver Enable Register Name:PIO_MDER Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Multi Drive Enable 0: No effect. 1: Enables Multi Drive on the I/O line. DS60001516A-page 374 2017 Microchip Technology Inc.
SAM9G20 28.6.19 PIO Multi-driver Disable Register Name:PIO_MDDR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Multi Drive Disable 0: No effect. 1: Disables Multi Drive on the I/O line. 2017 Microchip Technology Inc.
SAM9G20 28.6.20 PIO Multi-driver Status Register Name:PIO_MDSR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Multi Drive Status 0: The Multi Drive is disabled on the I/O line. The pin is driven at high and low level. 1: The Multi Drive is enabled on the I/O line.
SAM9G20 28.6.21 PIO Pull Up Disable Register Name:PIO_PUDR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Pull Up Disable 0: No effect. 1: Disables the pull up resistor on the I/O line. 2017 Microchip Technology Inc.
SAM9G20 28.6.22 PIO Pull Up Enable Register Name:PIO_PUER Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Pull Up Enable 0: No effect. 1: Enables the pull up resistor on the I/O line. DS60001516A-page 378 2017 Microchip Technology Inc.
SAM9G20 28.6.23 PIO Pull Up Status Register Name:PIO_PUSR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Pull Up Status 0: Pull Up resistor is enabled on the I/O line. 1: Pull Up resistor is disabled on the I/O line. 2017 Microchip Technology Inc.
SAM9G20 28.6.24 PIO Peripheral A Select Register Name:PIO_ASR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Peripheral A Select 0: No effect. 1: Assigns the I/O line to the Peripheral A function. DS60001516A-page 380 2017 Microchip Technology Inc.
SAM9G20 28.6.25 PIO Peripheral B Select Register Name:PIO_BSR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Peripheral B Select 0: No effect. 1: Assigns the I/O line to the peripheral B function. 2017 Microchip Technology Inc.
SAM9G20 28.6.26 PIO Peripheral A B Status Register Name:PIO_ABSR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Peripheral A B Status 0: The I/O line is assigned to the Peripheral A. 1: The I/O line is assigned to the Peripheral B.
SAM9G20 28.6.27 PIO Output Write Enable Register Name:PIO_OWER Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Output Write Enable 0: No effect. 1: Enables writing PIO_ODSR for the I/O line. 2017 Microchip Technology Inc.
SAM9G20 28.6.28 PIO Output Write Disable Register Name:PIO_OWDR Access:Write-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Output Write Disable 0: No effect. 1: Disables writing PIO_ODSR for the I/O line. DS60001516A-page 384 2017 Microchip Technology Inc.
SAM9G20 28.6.29 PIO Output Write Status Register Name:PIO_OWSR Access:Read-only 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 P0–P31: Output Write Status 0: Writing PIO_ODSR does not affect the I/O line. 1: Writing PIO_ODSR affects the I/O line. 2017 Microchip Technology Inc.
SAM9G20 29. Serial Peripheral Interface (SPI) 29.1 Overview The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides communication with external devices in Master or Slave Mode. It also enables communication between processors if an external processor is connected to the system. The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to other SPIs.
SAM9G20 29.3 Application Block Diagram Figure 29-2: Application Block Diagram: Single Master/Multiple Slave Implementation SPI Master SPCK SPCK MISO MISO MOSI MOSI NPCS0 NSS Slave 0 SPCK NPCS1 NPCS2 NC NPCS3 MISO Slave 1 MOSI NSS SPCK MISO Slave 2 MOSI NSS 29.
SAM9G20 29.6 Functional Description 29.6.1 Modes of Operation The SPI operates in Master Mode or in Slave Mode. Operation in Master Mode is programmed by writing at 1 the MSTR bit in the Mode Register. The pins NPCS0 to NPCS3 are all configured as outputs, the SPCK pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output by the transmitter. If the MSTR bit is written at 0, the SPI operates in Slave Mode.
SAM9G20 Figure 29-4: SPI Transfer Format (NCPHA = 0, 8 bits per transfer) 1 SPCK cycle (for reference) 2 3 4 5 8 7 6 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MISO (from slave) * MSB 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB LSB NSS (to slave) * Not defined but normally LSB of previous character transmitted. 29.6.3 Master Mode Operations When configured in Master Mode, the SPI operates on the clock generated by the internal programmable baud rate generator.
SAM9G20 29.6.3.1 Master Mode Block Diagram Figure 29-5: Master Mode Block Diagram SPI_CSR0..3 SCBR Baud Rate Generator MCK SPCK SPI Clock SPI_CSR0..3 BITS NCPHA CPOL LSB MISO SPI_RDR RDRF OVRES RD MSB Shift Register MOSI SPI_TDR TDRE TD SPI_CSR0..3 SPI_RDR CSAAT PCS PS NPCS3 PCSDEC SPI_MR PCS 0 NPCS2 Current Peripheral NPCS1 SPI_TDR NPCS0 PCS 1 MSTR MODF NPCS0 MODFDIS DS60001516A-page 390 2017 Microchip Technology Inc.
SAM9G20 29.6.3.2 Master Mode Flow Diagram Figure 29-6: Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
SAM9G20 29.6.3.3 Clock Generation The SPI Baud rate clock is generated by dividing the Master Clock (MCK), by a value between 1 and 255. This allows a maximum operating baud rate at up to Master Clock and a minimum operating baud rate of MCK divided by 255. Programming the SCBR field at 0 is forbidden. Triggering a transfer while SCBR is at 0 can lead to unpredictable results. At reset, SCBR is 0 and the user has to program it at a valid value before performing the first transfer.
SAM9G20 29.6.3.6 Peripheral Chip Select Decoding The user can program the SPI to operate with up to 15 peripherals by decoding the four Chip Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing the PCSDEC bit at 1 in the Mode Register (SPI_MR). When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select is driven low.
SAM9G20 29.6.3.8 Mode Fault Detection A mode fault is detected when the SPI is programmed in Master Mode and a low level is driven by an external master on the NPCS0/NSS signal. NPCS0, MOSI, MISO and SPCK must be configured in open drain through the PIO controller, so that external pull up resistors are needed to guarantee high level.
SAM9G20 29.
SAM9G20 29.7.1 SPI Control Register Name: SPI_CR Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – – – SPIDIS SPIEN SPIEN: SPI Enable 0: No effect. 1: Enables the SPI to transfer and receive data. SPIDIS: SPI Disable 0: No effect. 1: Disables the SPI. As soon as SPIDIS is set, SPI finishes its transfer.
SAM9G20 29.7.2 SPI Mode Register Name: SPI_MR Access: Read/Write 31 30 29 28 27 26 19 18 25 24 17 16 DLYBCS 23 22 21 20 – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 3 7 6 5 4 LLB – – MODFDIS PCS 2 1 0 PCSDEC PS MSTR MSTR: Master/Slave Mode 0: SPI is in Slave mode. 1: SPI is in Master mode. PS: Peripheral Select 0: Fixed Peripheral Select. 1: Variable Peripheral Select.
SAM9G20 PCS: Peripheral Chip Select This field is only used if Fixed Peripheral Select is active (PS = 0). If PCSDEC = 0: PCS = xxx0NPCS[3:0] = 1110 PCS = xx01NPCS[3:0] = 1101 PCS = x011NPCS[3:0] = 1011 PCS = 0111NPCS[3:0] = 0111 PCS = 1111forbidden (no peripheral is selected) (x = don’t care) If PCSDEC = 1: NPCS[3:0] output signals = PCS. DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS.
SAM9G20 29.7.3 SPI Receive Data Register Name: SPI_RDR Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 RD 7 6 5 4 RD RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero. PCS: Peripheral Chip Select In Master Mode only, these bits indicate the value on the NPCS pins at the end of a transfer. Otherwise, these bits read zero.
SAM9G20 29.7.4 SPI Transmit Data Register Name: SPI_TDR Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – LASTXFER 23 22 21 20 19 18 17 16 – – – – 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD 7 6 5 4 TD TD: Transmit Data Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the transmit data register in a right-justified format.
SAM9G20 29.7.
SAM9G20 TXEMPTY: Transmission Registers Empty 0: As soon as data is written in SPI_TDR. 1: SPI_TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the completion of such delay. SPIENS: SPI Enable Status 0: SPI is disabled. 1: SPI is enabled. Note 1: SPI_RCR, SPI_RNCR, SPI_TCR, SPI_TNCR are physically located in the PDC. DS60001516A-page 402 2017 Microchip Technology Inc.
SAM9G20 29.7.
SAM9G20 29.7.
SAM9G20 29.7.
SAM9G20 29.7.9 SPI Chip Select Register Name: SPI_CSR0... SPI_CSR3 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 3 2 1 0 CSAAT – NCPHA CPOL CPOL: Clock Polarity 0: The inactive state value of SPCK is logic level zero. 1: The inactive state value of SPCK is logic level one. CPOL is used to determine the inactive state value of the serial clock (SPCK).
SAM9G20 BITS Bits Per Transfer 1101 Reserved 1110 Reserved 1111 Reserved SCBR: Serial Clock Baud Rate In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the Master Clock MCK. The Baud rate is selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate: MCK SPCK Baudrate = --------------SCBR Programming the SCBR field at 0 is forbidden.
SAM9G20 30. Two-wire Interface (TWI) 30.1 Overview The Microchip Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and one data line with speeds of up to 400 Kbits per second, based on a byte-oriented transfer format. It can be used with any Microchip Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real Time Clock (RTC), Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few.
SAM9G20 30.3 Block Diagram Figure 30-1: Block Diagram APB Bridge TWCK PIO PMC MCK TWD Two-wire Interface TWI Interrupt 30.4 AIC Application Block Diagram Figure 30-2: Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Microchip TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp. Sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 30.4.
SAM9G20 30.5 30.5.1 Product Dependencies I/O Lines Both TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current source or pull-up resistor (see Figure 302). When the bus is free, both lines are high. The output stages of devices connected to the bus must have an open-drain or open-collector to perform the wired-AND function. TWD and TWCK pins may be multiplexed with PIO lines.
SAM9G20 • Multi-master receiver mode • Slave transmitter mode • Slave receiver mode These modes are described in the following sections. 30.6.3 Master Mode 30.6.3.1 Definition The Master is the device that starts a transfer, generates a clock and stops it. 30.6.3.2 Application Block Diagram Figure 30-5: Master Mode Typical Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Microchip TWI Serial EEPROM Slave 1 I²C RTC I²C LCD Controller I²C Temp.
SAM9G20 Figure 30-6: Master Write with On Data Byte S TWD DADR W A DATA A P TXCOMP TXRDY STOP sent automaticaly (ACK received and TXRDY = 1) Write THR (DATA) Figure 30-7: Master Write with Multiple Data Byte S TWD DADR W A DATA n A DATA n+5 A DATA n+x A P TXCOMP TXRDY Write THR (Data n) Figure 30-8: TWD S Write THR (Data n+1) Write THR (Data n+x) Last data sent STOP sent automaticaly (ACK received and TXRDY = 1) Master Write with One Byte Internal Address and Multiple Data Byt
SAM9G20 Figure 30-9: Master Read with One Data Byte TWD S DADR R A DATA N P TXCOMP Write START & STOP Bit RXRDY Read RHR Figure 30-10: TWD S Master Read with Multiple Data Bytes DADR R A DATA n A DATA (n+1) A DATA (n+m)-1 A DATA (n+m) N P TXCOMP Write START Bit RXRDY Read RHR DATA n Read RHR DATA (n+1) Read RHR DATA (n+m)-1 Read RHR DATA (n+m) Write STOP Bit after next-to-last data read RXRDY is used as Receive Ready for the PDC receive channel. 30.6.3.
SAM9G20 Figure 30-11: Master Write with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address S TWD DADR W A IADR(23:16) A IADR(15:8) A IADR(7:0) A W A IADR(15:8) A IADR(7:0) A DATA A W A IADR(7:0) A DATA A DATA A P Two bytes internal address S TWD DADR P One byte internal address S TWD DADR Figure 30-12: P Master Read with One, Two or Three Bytes Internal Address and One Data Byte Three bytes internal address S TWD DADR A W IADR
SAM9G20 • Data Receive with the PDC 1. Initialize the receive PDC (memory pointers, size - 1, etc.). 2. Configure the master mode (DADR, CKDIV, etc.). 3. Start the transfer by setting the PDC RXTEN bit. 4. Wait for the PDC end RX flag. 5. Disable the PDC by setting the PDC RXDIS bit. 30.6.3.8 Read/Write Flowcharts The flowcharts in the following figures provide examples of read and write operations. A polling or interrupt method can be used to check the status bits.
SAM9G20 Figure 30-15: TWI Write Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Internal address size (IADRSZ) - Transfer direction bit Write ==> bit MREAD = 0 Set the internal address TWI_IADR = address Load transmit register TWI_THR = Data to send Read Status register No TXRDY = 1? Yes Read Status
SAM9G20 Figure 30-16: TWI Write Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Write ==> bit MREAD = 0 No Internal address size = 0? Set the internal address TWI_IADR = address Yes Load Transmit register TWI_THR = Data to send Re
SAM9G20 Figure 30-17: TWI Read Operation with Single Data Byte without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Transfer direction bit Read ==> bit MREAD = 1 Start the transfer TWI_CR = START | STOP Read status register RXRDY = 1? No Yes Read Receive Holding Register Read Status register No TXCOMP = 1? Yes END DS60001516A-page 418
SAM9G20 Figure 30-18: TWI Read Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (IADRSZ) - Transfer direction bit Read ==> bit MREAD = 1 Set the internal address TWI_IADR = address Start the transfer TWI_CR = START | STOP Read Status register No RXRDY = 1? Yes Read Receive Holding regi
SAM9G20 Figure 30-19: TWI Read Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Read ==> bit MREAD = 1 Internal address size = 0? Set the internal address TWI_IADR = address Yes Start the transfer TWI_CR = START Read Status register
SAM9G20 30.6.4 30.6.4.1 Multi-master Mode Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop.
SAM9G20 Figure 30-20: Programmer Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master DATA sent by a master TWD DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Figure 30-21: Bus is considered as free Transfer is initiated Arbitration Cases TWCK TWD TWCK Data from a Master S 1 0 0 1 1 Data from TWI S 1 0 TWD S 1 0 0 1 P Arbitration is lost TWI stops sending data 1
SAM9G20 Figure 30-22: Multi-master Flowchart START Programm the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? Yes GACC = 1 ? No No SVREAD = 0 ? No No EOSACC = 1 ? TXRDY= 1 ? Yes Yes Yes No Write in TWI_THR TXCOMP = 1 ? RXRDY= 0 ? Yes No No No Yes Read TWI_RHR Need to perform a master access ? GENERAL CALL TREATMENT Yes Decoding of the programming sequence Prog seq OK ? No Change SADR Program the Master mode DADR + SVDIS + MSEN + CLK + R / W Read Status Register
SAM9G20 30.6.5 Slave Mode 30.6.5.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 30.6.5.2 Application Block Diagram Figure 30-23: Slave Mode Typical Application Block Diagram VDD R Master Host with TWI Interface 30.6.5.
SAM9G20 Clock stretching information is given by the SCLWS (Clock Wait state) bit. See Figure 30-27 and Figure 30-28. • General Call In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set. After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL and to decode the new address programming sequence. See Figure 30-26. 30.6.5.
SAM9G20 Figure 30-25: Write Access Ordered by a Master SADR does not match, TWI answers with a NACK S TWD ADR W NA DATA NA SADR matches, TWI answers with an ACK P/S/Sr SADR W A DATA Read RHR A A DATA NA S/Sr RXRDY SVACC SVREAD has to be taken into account only while SVACC is active SVREAD EOSVACC Note 1: When SVACC is low, the state of SVREAD becomes irrelevant. 2: RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read.
SAM9G20 Figure 30-27: Clock Synchronization in Read Mode TWI_THR S SADR DATA1 1 DATA0 R A DATA0 A DATA1 DATA2 A DATA2 XXXXXXX NA S 2 TWCK CLOCK is tied low by the TWI as long as THR is empty Write THR SCLWS TXRDY SVACC SVREAD As soon as a START is detected TXCOMP Ack or Nack from the master TWI_THR is transmitted to the shift register 1 The data is memorized in TWI_THR until a new value is written 2 The clock is stretched after the ACK, the state of TWD is undefined during clock
SAM9G20 2: SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mechanism is finished. • Reversal after a Repeated Start Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. Figure 30-29 describes the repeated start + reversal from Read to Write mode.
SAM9G20 30.6.5.7 Read/Write Flowcharts The flowchart shown in Figure 30-31 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first.
SAM9G20 30.
SAM9G20 30.7.1 TWI Control Register Name: TWI_CR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 – 5 SVDIS 4 SVEN 3 MSDIS 2 MSEN 1 STOP 0 START START: Send a START Condition 0: No effect. 1: A frame beginning with a START bit is transmitted according to the features defined in the mode register. This action is necessary when the TWI peripheral wants to read data from a slave.
SAM9G20 SWRST: Software Reset 0: No effect. 1: Equivalent to a system reset. DS60001516A-page 432 2017 Microchip Technology Inc.
SAM9G20 30.7.
SAM9G20 30.7.3 TWI Slave Mode Register Name: TWI_SMR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 SADR 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode. SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect.
SAM9G20 30.7.4 TWI Internal Address Register Name: TWI_IADR Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. 2017 Microchip Technology Inc.
SAM9G20 30.7.5 TWI Clock Waveform Generator Register Name: TWI_CWGR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 CKDIV 16 15 14 13 12 11 10 9 8 3 2 1 0 CHDIV 7 6 5 4 CLDIV TWI_CWGR is only used in Master mode.
SAM9G20 30.7.6 TWI Status Register Name: TWI_SR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXBUFE 14 RXBUFF 13 ENDTX 12 ENDRX 11 EOSACC 10 SCLWS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 SVREAD 2 TXRDY 1 RXRDY 0 TXCOMP TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0: During the length of the current frame.
SAM9G20 SVREAD: Slave Read (automatically set / reset) This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant. 0: Indicates that a write access is performed by a Master. 1: Indicates that a read access is performed by a Master. SVREAD behavior can be seen in Figure 30-24, Figure 30-25, Figure 30-29 and Figure 30-30. SVACC: Slave Access (automatically set / reset) This bit is only used in Slave mode. 0: TWI is not addressed.
SAM9G20 EOSACC: End Of Slave Access (clear on read) This bit is only used in Slave mode. 0: A slave access is being performing. 1: The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset. EOSACC behavior can be seen in Figure 30-29 and Figure 30-30. ENDRX: End of RX buffer This bit is only used in Master mode. 0: The Receive Counter Register has not reached 0 since the last write in TWI_RCR or TWI_RNCR.
SAM9G20 30.7.
SAM9G20 30.7.
SAM9G20 30.7.
SAM9G20 30.7.10 TWI Receive Holding Register Name: TWI_RHR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RXDATA RXDATA: Master or Slave Receive Holding Data 2017 Microchip Technology Inc.
SAM9G20 30.7.11 TWI Transmit Holding Register Name: TWI_THR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TXDATA TXDATA: Master or Slave Transmit Holding Data DS60001516A-page 444 2017 Microchip Technology Inc.
SAM9G20 31. Universal Synchronous Asynchronous Receiver Transmitter (USART) 31.1 Overview The Universal Synchronous Asynchronous Receiver Transceiver (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection.
SAM9G20 31.3 Application Block Diagram Figure 31-2: Application Block Diagram IrLAP PPP Modem Driver Serial Driver Field Bus Driver EMV Driver IrDA Driver USART RS232 Drivers RS232 Drivers RS485 Drivers Serial Port Differential Bus Smart Card Slot IrDA Transceivers Modem PSTN 31.
SAM9G20 31.5 31.5.1 Product Dependencies I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory.
SAM9G20 31.6 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes: • 5- to 9-bit full-duplex asynchronous serial communication - MSB- or LSB-first - 1, 1.
SAM9G20 Figure 31-3: Baud Rate Generator USCLKS CD MCK SCK 0 MCK/DIV SCK CD 1 Reserved 16-bit Counter 2 FIDI >1 3 1 0 0 0 SYNC OVER Sampling Divider 0 Baud Rate Clock 1 1 SYNC Sampling Clock USCLKS = 3 31.6.1.1 Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR).
SAM9G20 Table 31-2: Baud Rate Example (OVER = 0) (Continued) Source Clock (MHz) Expected Baud Rate (bit/s) Calculation Result CD Actual Baud Rate (bit/s) Error 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.10 65 38 461.54 0.16% 50 000 000 38 400 81.38 81 38 580.25 0.
SAM9G20 31.6.1.4 Baud Rate in Synchronous Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR. SelectedClock BaudRate = -------------------------------------CD In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 4.
SAM9G20 This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value.
SAM9G20 Figure 31-6: Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD D0 Start Bit D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed.
SAM9G20 bility, the encoding scheme can be configured using the TX_MPOL field in the US_MAN register. If the TX_MPOL field is set to zero (default), a logic zero is encoded with a zero-to-one transition and a logic one is encoded with a one-to-zero transition. If the TX_MPOL field is set to one, a logic one is encoded with a one-to-zero transition and a logic zero is encoded with a zero-to-one transition.
SAM9G20 Figure 31-10: Start Frame Delimiter Preamble Length is set to 0 SFD Manchester encoded data DATA Txd One bit start frame delimiter SFD Manchester encoded data DATA Txd SFD Manchester encoded data Command Sync start frame delimiter DATA Txd Data Sync start frame delimiter 31.6.3.3 Drift Compensation Drift compensation is available only in 16X oversampling mode. An hardware recovery system allows a larger clock drift.
SAM9G20 The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur.
SAM9G20 Figure 31-14: Asynchronous Start Bit Detection Sampling Clock (16 x) Manchester encoded data Txd Start Detection 1 2 3 4 The receiver is activated and starts Preamble and Frame Delimiter detection, sampling the data at one quarter and then three quarters. If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding with the same synchronization.
SAM9G20 31.6.3.6 Radio Interface: Manchester Encoded USART Application This section describes low data rate RF transmission systems and their integration with a Manchester encoded USART. These systems are based on transmitter and receiver ICs that support ASK and FSK modulation schemes. The goal is to perform full duplex radio transmission of characters using two different frequency carriers. See the configuration in Figure 31-17.
SAM9G20 Figure 31-19: FSK Modulator Output 1 0 0 1 NRZ stream Manchester encoded data default polarity unipolar output Txd FSK Modulator Output Uptstream Frequencies [F0, F0+offset] 31.6.3.7 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit.
SAM9G20 Figure 31-21: Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR Read US_RHR RXRDY OVRE 31.6.3.9 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see Section 31.6.3.10 Multidrop Mode. Even and odd parity bit generation and error detection are supported.
SAM9G20 Figure 31-22: Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE RXRDY 31.6.3.10 Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1.
SAM9G20 Figure 31-23: Timeguard Operations TG = 4 TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY Table 31-7 indicates the maximum length of a timeguard period that the transmitter can handle in relation to the function of the baud rate. Table 31-7: 31.6.3.
SAM9G20 If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. Figure 31-24 shows the block diagram of the Receiver Time-out feature.
SAM9G20 Figure 31-25: Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR FRAME RXRDY 31.6.3.14 Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0.
SAM9G20 31.6.3.15 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the Control Register (US_CR) with the bit RSTSTA at 1.
SAM9G20 31.6.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1. 31.6.4.
SAM9G20 Figure 31-32: T = 0 Protocol with Parity Error Baud Rate Clock Error I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1 Repetition 31.6.4.3 Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field. 31.6.4.
SAM9G20 Figure 31-33: Connection to IrDA Transceivers USART IrDA Transceivers Receiver Demodulator RXD Transmitter Modulator TXD RX TX The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. To receive IrDA signals, the following needs to be done: • Disable TX and Enable RX • Configure the TXD pin as PIO and set it as an output at 0 (to avoid LED emission). Disable the internal pull-up (better for power consumption).
SAM9G20 31.6.5.2 IrDA Baud Rate Table 31-10 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 31-10: IrDA Baud Rate Error Peripheral Clock Baud Rate (bit/s) CD Baud Rate Error Pulse Time (µs) 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.63 32 768 000 115 200 18 1.25% 1.63 40 000 000 115 200 22 1.38% 1.63 3 686 400 57 600 4 0.00% 3.
SAM9G20 Figure 31-35: IrDA Demodulator Operations MCK RXD Counter Value 6 Receiver Input 5 4 3 Pulse Rejected 2 6 6 5 4 3 2 1 0 Pulse Accepted As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly. 31.6.6 RS485 Mode The USART features the RS485 mode to enable line driver control.
SAM9G20 Figure 31-37: Example of RTS Drive with Timeguard TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY RTS 31.6.7 Modem Mode The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator).
SAM9G20 31.6.8 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 31.6.8.1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. Figure 31-38: Normal Mode Configuration RXD Receiver TXD Transmitter 31.6.8.
SAM9G20 Figure 31-41: Remote Loopback Mode Configuration Receiver 1 RXD TXD Transmitter 2017 Microchip Technology Inc.
SAM9G20 31.
SAM9G20 31.7.1 USART Control Register Name:US_CR Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RTSDIS 18 RTSEN 17 DTRDIS 16 DTREN 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. RXEN: Receiver Enable 0: No effect.
SAM9G20 STTTO: Start Time-out 0: No effect. 1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR. SENDA: Send Address 0: No effect. 1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set. RSTIT: Reset Iterations 0: No effect. 1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled. RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in US_CSR.
SAM9G20 31.7.
SAM9G20 PAR: Parity Type PAR Parity Type 0 0 0 Even parity 0 0 1 Odd parity 0 1 0 Parity forced to 0 (Space) 0 1 1 Parity forced to 1 (Mark) 1 0 x No parity 1 1 x Multidrop mode NBSTOP: Number of Stop Bits NBSTOP Asynchronous (SYNC = 0) Synchronous (SYNC = 1) 0 0 1 stop bit 1 stop bit 0 1 1.5 stop bits Reserved 1 0 2 stop bits 2 stop bits 1 1 Reserved Reserved CHMODE: Channel Mode CHMODE Mode Description 0 0 Normal Mode 0 1 Automatic Echo.
SAM9G20 DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted.
SAM9G20 31.7.
SAM9G20 31.7.
SAM9G20 31.7.
SAM9G20 31.7.6 USART Channel Status Register Name:US_CSR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 MANERR 23 CTS 22 DCD 21 DSR 20 RI 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled.
SAM9G20 TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register. ITER: Max number of Repetitions Reached 0: Maximum number of repetitions has not been reached since the last RSTSTA. 1: Maximum number of repetitions has been reached since the last RSTSTA. TXBUFE: Transmission Buffer Empty 0: The signal Buffer Empty from the Transmit PDC channel is inactive.
SAM9G20 MANERR: Manchester Error 0: No Manchester error has been detected since the last RSTSTA. 1: At least one Manchester error has been detected since the last RSTSTA. 2017 Microchip Technology Inc.
SAM9G20 31.7.7 USART Receive Holding Register Name:US_RHR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR RXCHR: Received Character Last character received if RXRDY is set. RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command. DS60001516A-page 486 2017 Microchip Technology Inc.
SAM9G20 31.7.8 USART Transmit Holding Register Name:US_THR Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. TXSYNH: Sync Field to be transmitted 0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC.
SAM9G20 31.7.
SAM9G20 31.7.10 USART Receiver Time-out Register Name:US_RTOR Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO TO: Time-out Value 0: The Receiver Time-out is disabled. 1–65535: The Receiver Time-out is enabled and the Time-out delay is TO x Bit Period. 2017 Microchip Technology Inc.
SAM9G20 31.7.11 USART Transmitter Timeguard Register Name:US_TTGR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1–255: The Transmitter timeguard is enabled and the timeguard delay is TG x Bit Period. DS60001516A-page 490 2017 Microchip Technology Inc.
SAM9G20 31.7.12 USART FI DI RATIO Register Name:US_FIDI Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1–2047: If ISO7816 mode is selected, the Baud Rate is the clock provided on SCK divided by FI_DI_RATIO. 2017 Microchip Technology Inc.
SAM9G20 31.7.13 USART Number of Errors Register Name:US_NER Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read. DS60001516A-page 492 2017 Microchip Technology Inc.
SAM9G20 31.7.14 USART IrDA FILTER Register Name:US_IF Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator. 2017 Microchip Technology Inc.
SAM9G20 31.7.
SAM9G20 DRIFT: Drift compensation 0: The USART can not recover from an important clock drift 1: The USART can recover from clock drift. The 16X clock mode must be enabled. 2017 Microchip Technology Inc.
SAM9G20 32. Synchronous Serial Controller (SSC) 32.1 Overview The Microchip Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider.
SAM9G20 32.3 Application Block Diagram Figure 32-2: Application Block Diagram OS or RTOS Driver Power Management Interrupt Management Test Management SSC Serial AUDIO 32.
SAM9G20 Figure 32-3: SSC Functional Block Diagram Transmitter MCK TK Input Clock Divider Transmit Clock Controller RX clock TF RF Start Selector TX clock Clock Output Controller TK Frame Sync Controller TF Transmit Shift Register TX PDC Transmit Holding Register APB TD Transmit Sync Holding Register Load Shift User Interface Receiver RK Input Receive Clock RX Clock Controller TX Clock RF TF Start Selector Interrupt Control RK Frame Sync Controller RF Receive Shift Register RX PD
SAM9G20 32.6.1.1 Clock Divider Figure 32-4: Divided Clock Block Diagram Clock Divider SSC_CMR MCK /2 12-bit Counter Divided Clock The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive.
SAM9G20 Figure 32-6: Transmitter Clock Management TK (pin) Clock Output Tri-state Controller MUX Receiver Clock Divider Clock Data Transfer CKO CKS 32.6.1.3 INV MUX Tri-state Controller CKI CKG Transmitter Clock Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register).
SAM9G20 In addition, the maximum clock speed allowed on the TK pin is: - Master Clock divided by 6 if Transmit Frame Synchro is input - Master Clock divided by 2 if Transmit Frame Synchro is output 32.6.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See Section 32.6.4 Start.
SAM9G20 Figure 32-9: Receiver Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS RF Receiver Clock TF Start Selector SSC_RFMR.MSBF SSC_RFMR.DATNB Receive Shift Register SSC_RSHR SSC_RHR SSC_RFMR.FSLEN SSC_RFMR.DATLEN RD SSC_RCMR.STTDLY 32.6.4 Start The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection (START) field of SSC_TCMR and in the Receive Start Selection (START) field of SSC_RCMR.
SAM9G20 Figure 32-10: Transmit Start Mode TK TF (Input) Start = Low Level on TF Start = Falling Edge on TF Start = High Level on TF Start = Rising Edge on TF Start = Level Change on TF Start = Any Edge on TF TD (Output) TD (Output) X BO B1 STTDLY BO X B1 STTDLY BO X TD (Output) B1 STTDLY TD (Output) BO X B1 STTDLY TD (Output) BO X B1 BO B1 STTDLY TD (Output) X B1 BO BO B1 STTDLY Figure 32-11: Receive Pulse/Edge Start Modes RK RF (Input) Start = Low Level on RF Start = Fa
SAM9G20 32.6.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform. • Programmable low or high levels during data transfer are supported. • Programmable high levels before the start of data transfers or toggling are also supported.
SAM9G20 32.6.7 Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR).
SAM9G20 Figure 32-14: Transmit Frame Format in Continuous Mode Start Data TD Default Data From SSC_THR From SSC_THR DATLEN DATLEN Start: 1. TXEMPTY set to 1 2. Write into the SSC_THR Note 1: STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode.
SAM9G20 Figure 32-16: Interrupt Block Diagram SSC_IMR SSC_IER PDC SSC_IDR Set Clear TXBUFE ENDTX Transmitter TXRDY TXEMPTY TXSYNC Interrupt Control RXBUFF ENDRX SSC Interrupt Receiver RXRDY OVRUN RXSYNC 32.7 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here.
SAM9G20 Figure 32-18: Codec Application Block Diagram Serial Data Clock (SCLK) TK Frame sync (FSYNC) TF CODEC Serial Data Out TD SSC Serial Data In RD RF RK Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Dend Serial Data Out Serial Data In Figure 32-19: Time Slot Application Block Diagram SCLK TK FSYNC TF CODEC First Time Slot Data Out TD SSC RD Data in RF RK CODEC Second Time Slot Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Second Time Slot Dend
SAM9G20 32.
SAM9G20 32.8.1 SSC Control Register Name:SSC_CR Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SWRST 14 – 13 – 12 – 11 – 10 – 9 TXDIS 8 TXEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXDIS 0 RXEN RXEN: Receive Enable 0: No effect. 1: Enables Receive if RXDIS is not set. RXDIS: Receive Disable 0: No effect. 1: Disables Receive. If a character is currently being received, disables at end of current character reception.
SAM9G20 32.8.2 SSC Clock Mode Register Name:SSC_CMR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 3 1 0 DIV 2 DIV DIV: Clock Divider 0: The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 x 4095 = MCK/8190. 2017 Microchip Technology Inc.
SAM9G20 32.8.
SAM9G20 START: Receive Start Selection START Receive Start 0x0 Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
SAM9G20 32.8.4 SSC Receive Frame Mode Register Name:SSC_RFMR Access:Read/Write 31 FSLEN_EXT 30 FSLEN_EXT 29 FSLEN_EXT 28 FSLEN_EXT 27 – 26 – 23 – 22 21 FSOS 20 19 18 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 LOOP 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits.
SAM9G20 FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register. FSEDGE Frame Sync Edge Detection 0x0 Positive Edge Detection 0x1 Negative Edge Detection FSLEN_EXT: FSLEN Field Extension Extends FSLEN field. For details, refer to FSLEN bit description above. 2017 Microchip Technology Inc.
SAM9G20 32.8.
SAM9G20 START: Transmit Start Selection START Transmit Start 0x0 Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data.
SAM9G20 32.8.6 SSC Transmit Frame Mode Register Name:SSC_TFMR Access:Read/Write 31 FSLEN_EXT 30 FSLEN_EXT 29 FSLEN_EXT 28 FSLEN_EXT 27 – 26 – 23 FSDEN 22 21 FSOS 20 19 18 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 DATDEF 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits.
SAM9G20 FSOS: Transmit Frame Sync Output Selection FSOS Selected Transmit Frame Sync Signal TF Pin 0x0 None 0x1 Negative Pulse Output 0x2 Positive Pulse Output 0x3 Driven Low during data transfer Output 0x4 Driven High during data transfer Output 0x5 Toggling at each start of data transfer Output 0x6–0x7 Reserved Input-only Undefined FSDEN: Frame Sync Data Enable 0: The TD line is driven with the default value during the Transmit Frame Sync signal.
SAM9G20 32.8.7 SSC Receive Holding Register Name:SSC_RHR Access:Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR. DS60001516A-page 520 2017 Microchip Technology Inc.
SAM9G20 32.8.8 SSC Transmit Holding Register Name:SSC_THR Access:Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TDAT 23 22 21 20 TDAT 15 14 13 12 TDAT 7 6 5 4 TDAT TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR. 2017 Microchip Technology Inc.
SAM9G20 32.8.9 SSC Receive Synchronization Holding Register Name:SSC_RSHR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RSDAT 7 6 5 4 RSDAT RSDAT: Receive Synchronization Data DS60001516A-page 522 2017 Microchip Technology Inc.
SAM9G20 32.8.10 SSC Transmit Synchronization Holding Register Name:SSC_TSHR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TSDAT 7 6 5 4 TSDAT TSDAT: Transmit Synchronization Data 2017 Microchip Technology Inc.
SAM9G20 32.8.11 SSC Receive Compare 0 Register Name:SSC_RC0R Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CP0 7 6 5 4 CP0 CP0: Receive Compare Data 0 DS60001516A-page 524 2017 Microchip Technology Inc.
SAM9G20 32.8.12 SSC Receive Compare 1 Register Name:SSC_RC1R Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CP1 7 6 5 4 CP1 CP1: Receive Compare Data 1 2017 Microchip Technology Inc.
SAM9G20 32.8.13 SSC Status Register Name:SSC_SR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RXEN 16 TXEN 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY TXRDY: Transmit Ready 0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1: SSC_THR is empty.
SAM9G20 CP1: Compare 1 0: A compare 1 has not occurred since the last read of the Status Register. 1: A compare 1 has occurred since the last read of the Status Register. TXSYN: Transmit Sync 0: A Tx Sync has not occurred since the last read of the Status Register. 1: A Tx Sync has occurred since the last read of the Status Register. RXSYN: Receive Sync 0: An Rx Sync has not occurred since the last read of the Status Register. 1: An Rx Sync has occurred since the last read of the Status Register.
SAM9G20 32.8.14 SSC Interrupt Enable Register Name:SSC_IER Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY TXRDY: Transmit Ready Interrupt Enable 0: No effect. 1: Enables the Transmit Ready Interrupt. TXEMPTY: Transmit Empty Interrupt Enable 0: No effect. 1: Enables the Transmit Empty Interrupt.
SAM9G20 CP1: Compare 1 Interrupt Enable 0: No effect. 1: Enables the Compare 1 Interrupt. TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Enables the Tx Sync Interrupt. RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Enables the Rx Sync Interrupt. 2017 Microchip Technology Inc.
SAM9G20 32.8.15 SSC Interrupt Disable Register Name:SSC_IDR Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY TXRDY: Transmit Ready Interrupt Disable 0: No effect. 1: Disables the Transmit Ready Interrupt. TXEMPTY: Transmit Empty Interrupt Disable 0: No effect. 1: Disables the Transmit Empty Interrupt.
SAM9G20 CP1: Compare 1 Interrupt Disable 0: No effect. 1: Disables the Compare 1 Interrupt. TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Disables the Tx Sync Interrupt. RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Disables the Rx Sync Interrupt. 2017 Microchip Technology Inc.
SAM9G20 32.8.16 SSC Interrupt Mask Register Name:SSC_IMR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY TXRDY: Transmit Ready Interrupt Mask 0: The Transmit Ready Interrupt is disabled. 1: The Transmit Ready Interrupt is enabled.
SAM9G20 CP1: Compare 1 Interrupt Mask 0: The Compare 1 Interrupt is disabled. 1: The Compare 1 Interrupt is enabled. TXSYN: Tx Sync Interrupt Mask 0: The Tx Sync Interrupt is disabled. 1: The Tx Sync Interrupt is enabled. RXSYN: Rx Sync Interrupt Mask 0: The Rx Sync Interrupt is disabled. 1: The Rx Sync Interrupt is enabled. 2017 Microchip Technology Inc.
SAM9G20 33. Timer Counter (TC) 33.1 Overview The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user.
SAM9G20 33.
SAM9G20 33.3 Pin Name List Table 33-3: TC pin list Pin Name Description Type TCLK0–TCLK2 External Clock Input Input TIOA0–TIOA2 I/O Line A I/O TIOB0–TIOB2 I/O Line B I/O 33.4 33.4.1 Product Dependencies I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. 33.4.
SAM9G20 Figure 33-2: Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TCLK0 TIOA1 XC0 TIOA2 TIOA0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 XC0 = TCLK2 TIOA0 TIOA1 XC1 TIOA2 XC2 = TCLK2 TIOB1 SYNC Timer/Counter Channel 2 TC2XC2S XC0 = TCLK0 TCLK2 TIOA2 XC1 = TCLK1 TIOA0 XC2 TIOB2 TIOA1 SYNC Figure 33-3: Clock Selection TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 CLKI TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 Selected Clock XC0 XC1 XC2 BURST 1 2017
SAM9G20 33.5.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 33-4. • The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR.
SAM9G20 Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 33.5.7 Capture Operating Mode This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register).
DS60001516A-page 540 MTIOA MTIOB 1 If RA is not loaded or RB is Loaded Edge Detector ETRGEDG SWTRG Timer/Counter Channel ABETRG BURST S R OVF LDRB Edge Detector Edge Detector Capture Register A LDBSTOP R S CLKEN LDRA If RA is Loaded CPCTRG 16-bit Counter RESET Trig CLK Q Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR TIOA TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 CLKI Compare RC = Register C COVFS INT Figure 33-5: TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK
SAM9G20 33.5.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR).
DS60001516A-page 542 TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 EEVT BURST Timer/Counter Channel Edge Detector EEVTEDG SWTRG ENETRG CLKI Trig CLK R S OVF WAVSEL RESET 16-bit Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC TIOB MTIOB TIOA MTIOA Figure 33-6: Output Control
SAM9G20 33.5.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 33-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 33-8. RC Compare cannot be programmed to generate a trigger in this configuration.
SAM9G20 33.5.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 33-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 33-10.
SAM9G20 33.5.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 33-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 33-12.
SAM9G20 33.5.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 33-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 33-14.
SAM9G20 33.5.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined.
SAM9G20 33.
SAM9G20 33.6.1 TC Block Control Register Name:TC_BCR Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – SYNC SYNC: Synchro Command 0: No effect. 1: Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. 2017 Microchip Technology Inc.
SAM9G20 33.6.
SAM9G20 33.6.3 TC Channel Control Register Name:TC_CCRx [x=0..2] Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – SWTRG CLKDIS CLKEN CLKEN: Counter Clock Enable Command 0: No effect. 1: Enables the clock if CLKDIS is not 1. CLKDIS: Counter Clock Disable Command 0: No effect. 1: Disables the clock.
SAM9G20 33.6.4 TC Channel Mode Register: Capture Mode Name:TC_CMRx [x=0..
SAM9G20 ETRGEDG: External Trigger Edge Selection ETRGEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge ABETRG: TIOA or TIOB External Trigger Selection 0: TIOB is used as an external trigger. 1: TIOA is used as an external trigger. CPCTRG: RC Compare Trigger Enable 0: RC Compare has no effect on the counter and its clock. 1: RC Compare resets the counter and starts the counter clock. WAVE 0: Capture Mode is enabled. 1: Capture Mode is disabled (Waveform Mode is enabled).
SAM9G20 33.6.5 TC Channel Mode Register: Waveform Mode Name:TC_CMRx [x=0..
SAM9G20 EEVTEDG: External Event Edge Selection EEVTEDG Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge EEVT: External Event Selection EEVT Signal selected as external event TIOB Direction 0 0 TIOB input (1) 0 1 XC0 output 1 0 XC1 output 1 1 XC2 output Note 1: If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs.
SAM9G20 AEEVT: External Event Effect on TIOA AEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle ASWTRG: Software Trigger Effect on TIOA ASWTRG Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle BCPB: RB Compare Effect on TIOB BCPB Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle BCPC: RC Compare Effect on TIOB BCPC Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle BEEVT: External Event Effect on TIOB BEEVT Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle BS
SAM9G20 33.6.6 TC Counter Value Register Name:TC_CVx [x=0..2] Access:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 CV 7 6 5 4 CV CV: Counter Value CV contains the counter value in real time. 2017 Microchip Technology Inc.
SAM9G20 33.6.7 TC Register A Name:TC_RAx [x=0..2] Access:Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RA 7 6 5 4 RA RA: Register A RA contains the Register A value in real time. DS60001516A-page 558 2017 Microchip Technology Inc.
SAM9G20 33.6.8 TC Register B Name:TC_RBx [x=0..2] Access:Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RB 7 6 5 4 RB RB: Register B RB contains the Register B value in real time. 2017 Microchip Technology Inc.
SAM9G20 33.6.9 TC Register C Name:TC_RCx [x=0..2] Access:Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RC 7 6 5 4 RC RC: Register C RC contains the Register C value in real time. DS60001516A-page 560 2017 Microchip Technology Inc.
SAM9G20 33.6.10 TC Status Register Name:TC_SRx [x=0..2] Access:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – MTIOB MTIOA CLKSTA 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS COVFS: Counter Overflow Status 0: No counter overflow has occurred since the last read of the Status Register.
SAM9G20 MTIOA: TIOA Mirror 0: TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1: TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. MTIOB: TIOB Mirror 0: TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1: TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high.
SAM9G20 33.6.11 TC Interrupt Enable Register Name:TC_IERx [x=0..2] Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS COVFS: Counter Overflow 0: No effect. 1: Enables the Counter Overflow Interrupt. LOVRS: Load Overrun 0: No effect. 1: Enables the Load Overrun Interrupt.
SAM9G20 33.6.12 TC Interrupt Disable Register Name:TC_IDRx [x=0..2] Access:Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS COVFS: Counter Overflow 0: No effect. 1: Disables the Counter Overflow Interrupt. LOVRS: Load Overrun 0: No effect. 1: Disables the Load Overrun Interrupt (if WAVE = 0).
SAM9G20 33.6.13 TC Interrupt Mask Register Name:TC_IMRx [x=0..2] Access:Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS COVFS: Counter Overflow 0: The Counter Overflow Interrupt is disabled. 1: The Counter Overflow Interrupt is enabled. LOVRS: Load Overrun 0: The Load Overrun Interrupt is disabled.
SAM9G20 34. MultiMedia Card Interface (MCI) 34.1 Overview The MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC) Specification V3.11, the SDIO Specification V1.1 and the SD Memory Card Specification V1.0. The MCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead.
SAM9G20 34.3 Application Block Diagram Figure 34-2: Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer MCI Interface 1 2 3 4 5 6 78 1234567 9 SDCard MMC 34.4 Pin Name List Table 34-1: I/O Lines Description Pin Name(2) Pin Description Type(1) Comments MCCDA/MCCDB Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO MCCK Clock I/O CLK of an MMC or SD Card/SDIO MCDA0–MCDA3 Data 0..3 of Slot A I/O/PP MCDB0–MCDB3 Data 0..
SAM9G20 34.5.3 Interrupt The MCI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the MCI interrupt requires programming the AIC before configuring the MCI. 34.6 Bus Topology Figure 34-3: Multimedia Memory Card Bus Topology 1234567 MMC The MultiMedia Card communication is based on a 7-pin serial bus interface. It has three communication lines and four supply lines.
SAM9G20 Figure 34-5: SD Memory Card Bus Topology 1 2 3 4 5 6 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 34-3.
SAM9G20 SD Card Bus Connections with Two Slots 1 2 3 4 5 6 78 Figure 34-7: MCDA0 - MCDA3 MCCK 1 2 3 4 5 6 78 9 MCCDA SD CARD 1 MCDB0 - MCDB3 9 MCCDB SD CARD 2 Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK,MCCDA to MCIx_CDA, MCDAy to MCIx_DAy, MCCDB to MCIx_CDB, MCDBy to MCIx_DBy.
SAM9G20 34.7 MultiMedia Card Operations After a power-on reset, the cards are initialized by a special message-based MultiMedia Card bus protocol. Each message is represented by one of the following tokens: • Command: A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line.
SAM9G20 Table 34-4: ALL_SEND_CID Command Description CMD Index Type Argument Resp Abbreviation Command Description CMD2 bcr [31:0] stuff bits R2 ALL_SEND_CID Asks all cards to send their CID numbers on the CMD line Note: bcr means broadcast command with response.
SAM9G20 Figure 34-9: Command/Response Functional Flow Diagram Set the command argument MCI_ARGR = Argument(1) Set the command MCI_CMDR = Command Read MCI_SR Wait for command ready status flag 0 CMDRDY 1 Check error bits in the status register (1) Yes Status error flags? Read response if required RETURN ERROR(1) RETURN OK Note 1: If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the MultiMedia Card specification). 34.7.
SAM9G20 The number of blocks for the read (or write) multiple block operation is not defined. The card will continuously transfer (or program) data blocks until a stop transmission command is received. • Multiple block read (or write) with pre-defined block count (since version 3.1 and higher): The card will transfer (or program) the requested number of data blocks and terminate the transaction.
SAM9G20 Figure 34-10: Read Functional Flow Diagram Send SELECT/DESELECT_CARD (1) command to select the card Send SET_BLOCKLEN command(1) No Yes Read with PDC Reset the PDCMODE bit MCI_MR &= ~PDCMODE Set the block length (in bytes) MCI_MR |= (BlockLenght <<16)(2) Set the block count (if necessary) MCI_BLKR |= (BlockCount << 0) Set the PDCMODE bit MCI_MR |= PDCMODE Set the block length (in bytes) (2) MCI_BLKR |= (BlockLength << 16) Configure the PDC channel MCI_RPR = Data Buffer Address MCI_RCR = Block
SAM9G20 34.7.4 Write Operation In write operation, the MCI Mode Register (MCI_MR) is used to define the padding value when writing non-multiple block size. If the bit PDCPADV is 0, then 0x00 value is used when padding data, otherwise 0xFF is used. If set, the bit PDCMODE enables PDC transfer. The following flowchart shows how to write a single block with or without use of PDC facilities (see Figure 34-11).
SAM9G20 Figure 34-11: Write Functional Flow Diagram Send SELECT/DESELECT_CARD command(1) to select the card Send SET_BLOCKLEN command(1) Yes No Write using PDC Reset the PDCMODE bit MCI_MR &= ~PDCMODE Set the block length (in bytes) MCI_MR |= (BlockLenght <<16)(2) Set the block count (if necessary) MCI_BLKR |= (BlockCount << 0) Set the PDCMODE bit MCI_MR |= PDCMODE Set the block length (in bytes) MCI_BLKR |= (BlockLength << 16)(2) Configure the PDC channel MCI_TPR = Data Buffer Address to write MCI_T
SAM9G20 The flowchart in Figure 34-12 shows how to manage a multiple write block transfer with the PDC. Polling or interrupt method can be used to wait for the end of write according to the contents of the MCI_IMR.
SAM9G20 34.8 SD/SDIO Card Operations The MultiMedia Card Interface allows processing of SD Memory (Secure Digital Memory Card) and SDIO (SD Input Output) Card commands. SD/SDIO cards are based on the Multi Media Card (MMC) format, but are physically slightly thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental overwriting and security features.
SAM9G20 34.
SAM9G20 34.9.1 MCI Control Register Name: MCI_CR Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 SWRST – – – PWSDIS PWSEN MCIDIS MCIEN MCIEN: Multi-Media Interface Enable 0: No effect. 1: Enables the Multi-Media Interface if MCDIS is 0. MCIDIS: Multi-Media Interface Disable 0: No effect. 1: Disables the Multi-Media Interface.
SAM9G20 34.9.2 MCI Mode Register Name: MCI_MR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 BLKLEN 23 22 21 20 BLKLEN 15 14 13 12 11 PDCMODE PDCPADV PDCFBYTE WRPROOF RDPROOF 7 6 5 4 3 PWSDIV 2 1 0 CLKDIV CLKDIV: Clock Divider Multimedia Card Interface clock (MCCK or MCI_CK) is Master Clock (MCK) divided by (2*(CLKDIV+1)). PWSDIV: Power Saving Divider Multimedia Card Interface clock is divided by 2(PWSDIV) + 1 when entering Power Saving Mode.
SAM9G20 BLKLEN: Data Block Length This field determines the size of the data block. This field is also accessible in the MCI Block Register (MCI_BLKR). Bits 16 and 17 must be set to 0 if PDCFBYTE is disabled. Note: In SDIO Byte mode, BLKLEN field is not used. 2017 Microchip Technology Inc.
SAM9G20 34.9.3 MCI Data Timeout Register Name: MCI_DTOR Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – DTOMUL DTOCYC DTOCYC: Data Timeout Cycle Number DTOMUL: Data Timeout Multiplier These fields determine the maximum number of Master Clock cycles that the MCI waits between two data block transfers. It equals (DTOCYC x Multiplier).
SAM9G20 34.9.4 MCI SDCard/SDIO Register Name: MCI_SDCR Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 1 7 6 5 4 3 2 SDCBUS – – – – – 0 SDCSEL SDCSEL: SDCard/SDIO Slot SDCSEL SDCard/SDIO Slot 0 0 Slot A is selected.
SAM9G20 34.9.5 MCI Argument Register Name: MCI_ARGR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ARG 23 22 21 20 ARG 15 14 13 12 ARG 7 6 5 4 ARG ARG: Command Argument DS60001516A-page 586 2017 Microchip Technology Inc.
SAM9G20 34.9.6 MCI Command Register Name: MCI_CMDR Access: Write-only 31 30 29 28 27 26 – – – – – – 23 22 21 20 19 – – 15 14 13 12 11 – – – MAXLAT OPDCMD 6 5 4 3 7 18 TRTYP 25 24 IOSPCMD 17 16 TRDIR RSPTYP 10 TRCMD 9 8 SPCMD 2 1 0 CMDNB This register is write-protected while CMDRDY is 0 in MCI_SR. If an Interrupt command is sent, this register is only writeable by an interrupt response (field SPCMD).
SAM9G20 MAXLAT: Max Latency for Command to Response 0: 5-cycle max latency 1: 64-cycle max latency TRCMD: Transfer Command TRCMD Transfer Type 0 0 No data transfer 0 1 Start data transfer 1 0 Stop data transfer 1 1 Reserved TRDIR: Transfer Direction 0: Write 1: Read TRTYP: Transfer Type TRTYP Transfer Type 0 0 0 MMC/SDCard Single Block 0 0 1 MMC/SDCard Multiple Block 0 1 0 MMC Stream 0 1 1 Reserved 1 0 0 SDIO Byte 1 0 1 SDIO Block 1 1 0 Reserved 1 1 1 Reserved
SAM9G20 34.9.7 MCI Block Register Name: MCI_BLKR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BLKLEN 23 22 21 20 BLKLEN 15 14 13 12 BCNT 7 6 5 4 BCNT BCNT: MMC/SDIO Block Count - SDIO Byte Count This field determines the number of data byte(s) or block(s) to transfer.
SAM9G20 34.9.8 MCI Response Register Name: MCI_RSPR Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RSP 23 22 21 20 RSP 15 14 13 12 RSP 7 6 5 4 RSP RSP: Response Note: The response register can be read by N accesses at the same MCI_RSPR or at consecutive addresses (0x20 to 0x2C). N depends on the size of the response. DS60001516A-page 590 2017 Microchip Technology Inc.
SAM9G20 34.9.9 MCI Receive Data Register Name: MCI_RDR Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA 23 22 21 20 DATA 15 14 13 12 DATA 7 6 5 4 DATA DATA: Data to Read 2017 Microchip Technology Inc.
SAM9G20 34.9.10 MCI Transmit Data Register Name: MCI_TDR Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA 23 22 21 20 DATA 15 14 13 12 DATA 7 6 5 4 DATA DATA: Data to Write DS60001516A-page 592 2017 Microchip Technology Inc.
SAM9G20 34.9.11 MCI Status Register Name: MCI_SR Access: Read-only 31 30 29 28 27 26 25 24 UNRE OVRE – – – – – – 23 22 21 20 19 18 17 16 – DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE 15 14 13 12 11 10 9 8 TXBUFE RXBUFF – – - - SDIOIRQB SDIOIRQA 7 6 5 4 3 2 1 0 ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY CMDRDY: Command Ready 0: A command is in progress. 1: The last command has been sent. Cleared when writing in the MCI_CMDR.
SAM9G20 ENDTX: End of TX Buffer 0: The Transmit Counter Register has not reached 0 since the last write in MCI_TCR or MCI_TNCR. 1: The Transmit Counter Register has reached 0 since the last write in MCI_TCR or MCI_TNCR. Note: BLKE and NOTBUSY flags can be used to check that the data has been successfully transmitted on the data lines and not only transferred from the PDC to the MCI Controller. RXBUFF: RX Buffer Full 0: MCI_RCR or MCI_RNCR has a value other than 0.
SAM9G20 SDIOIRQA: SDIO Interrupt for Slot A 0: No interrupt detected on SDIO Slot A. 1: A SDIO Interrupt on Slot A has reached. Cleared when reading the MCI_SR. SDIOIRQB: SDIO Interrupt for Slot B 0: No interrupt detected on SDIO Slot B. 1: A SDIO Interrupt on Slot B has reached. Cleared when reading the MCI_SR. RXBUFF: RX Buffer Full 0: MCI_RCR or MCI_RNCR has a value other than 0. 1: Both MCI_RCR and MCI_RNCR have a value of 0. TXBUFE: TX Buffer Empty 0: MCI_TCR or MCI_TNCR has a value other than 0.
SAM9G20 34.9.
SAM9G20 34.9.
SAM9G20 34.9.
SAM9G20 35. Ethernet MAC 10/100 (EMAC) 35.1 Overview The EMAC module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 standard using an address checker, statistics and control registers, receive and transmit blocks, and a DMA interface. The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash register for matching multicast and unicast addresses.
SAM9G20 35.3 Functional Description The MACB has several clock domains: • • • System bus clock (AHB and APB): DMA and register blocks Transmit clock: transmit block Receive clock: receive and address checker blocks The only system constraint is 160 MHz for the system bus clock, above which MDC would toggle at above 2.5 MHz. The system bus clock must run at least as fast as the receive clock and transmit clock (25 MHz at 100 Mbps, and 2.5 MHz at 10 Mbps).
SAM9G20 35.3.2.2 Receive Buffers Received frames, including CRC/FCS optionally, are written to receive buffers stored in memory. Each receive buffer is 128 bytes long. The start location for each receive buffer is stored in memory in a list of receive buffer descriptors at a location pointed to by the receive buffer queue pointer register. The receive buffer start location is a word address.
SAM9G20 To receive frames, the buffer descriptors must be initialized by writing an appropriate address to bits 31 to 2 in the first word of each list entry. Bit zero must be written with zero. Bit one is the wrap bit and indicates the last entry in the list. The start location of the receive buffer descriptor list must be written to the receive buffer queue pointer register before setting the receive enable bit in the network control register to enable receive.
SAM9G20 The transmit buffer queue pointer register must not be written while transmit is active. If a new value is written to the transmit buffer queue pointer register, the queue pointer resets itself to point to the beginning of the new queue. If transmit is disabled by writing to bit 3 of the network control, the transmit buffer queue pointer register resets to point to the beginning of the transmit queue. Note that disabling receive does not have the same effect on the receive queue pointer.
SAM9G20 35.3.3 Transmit Block This block transmits frames in accordance with the Ethernet IEEE 802.3 CSMA/CD protocol. Frame assembly starts by adding preamble and the start frame delimiter. Data is taken from the transmit FIFO a word at a time. Data is transmitted least significant nibble first. If necessary, padding is added to increase the frame length to 60 bytes. CRC is calculated as a 32-bit polynomial.
SAM9G20 The enable bit for jumbo frames in the network configuration register allows the EMAC to receive jumbo frames of up to 10240 bytes in size. This operation does not form part of the IEEE802.3 specification and is disabled by default. When jumbo frames are enabled, frames received with a frame size greater than 10240 bytes are discarded. 35.3.6 Address Checking Block The address checking (or filter) block indicates to the DMA block which receive frames should be copied to memory.
SAM9G20 35.3.8 Hash Addressing The hash address register is 64 bits long and takes up two locations in the memory map. The least significant bits are stored in hash register bottom and the most significant bits in hash register top. The unicast hash enable and the multicast hash enable bits in the network configuration register enable the reception of hash matched frames. The destination address is reduced to a 6-bit index into the 64-bit hash register using the following hash function.
SAM9G20 35.3.12 PHY Maintenance The register EMAC_MAN enables the EMAC to communicate with a PHY by means of the MDIO interface. It is used during auto-negotiation to ensure that the EMAC and the PHY are configured for the same speed and duplex configuration. The PHY maintenance register is implemented as a shift register.
SAM9G20 35.4 35.4.1 35.4.1.1 Programming Interface Initialization Configuration Initialization of the EMAC configuration (e.g., loop-back mode, frequency ratios) must be done while the transmit and receive circuits are disabled. See the description of the network control register and network configuration register earlier in this document. To change loop-back mode, the following sequence of operations must be followed: 1. 2. 3. Write to network control register to disable transmit and receive circuits.
SAM9G20 3. 4. 5. If fewer than 1024 buffers are defined, the last descriptor must be marked with the wrap bit — bit 30 in word 1 set to 1. Write address of transmit buffer descriptor entry to EMAC register transmit_buffer queue pointer. The transmit circuits can then be enabled by writing to the network control register. 35.4.1.4 Address Matching The EMAC register-pair hash address and the four specific address register-pairs must be written with the required values.
SAM9G20 35.
SAM9G20 Table 35-6: Register Mapping (Continued) Offset Register Name Access Reset 0x90 Hash Register Bottom [31:0] Register EMAC_HRB Read/Write 0x0000_0000 0x94 Hash Register Top [63:32] Register EMAC_HRT Read/Write 0x0000_0000 0x98 Specific Address 1 Bottom Register EMAC_SA1B Read/Write 0x0000_0000 0x9C Specific Address 1 Top Register EMAC_SA1T Read/Write 0x0000_0000 0xA0 Specific Address 2 Bottom Register EMAC_SA2B Read/Write 0x0000_0000 0xA4 Specific Address 2 Top Regist
SAM9G20 35.5.1 Network Control Register Name:EMAC_NCR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 THALT 9 TSTART 8 BP 7 WESTAT 6 INCSTAT 5 CLRSTAT 4 MPE 3 TE 2 RE 1 LLB 0 LB LB: LoopBack Asserts the loopback signal to the PHY. LLB: Loopback local Connects txd to rxd, tx_en to rx_dv, forces full duplex and drives rx_clk and tx_clk with pclk divided by 4.
SAM9G20 35.5.2 Network Configuration Register Name:EMAC_NCFG Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 IRXFCS 18 EFRHD 17 DRFCS 16 RLCE 14 13 PAE 12 RTY 11 10 9 – 8 BIG 5 NBC 4 CAF 3 JFRAME 2 – 1 FD 0 SPD 15 RBOF 7 UNI 6 MTI CLK SPD: Speed Set to 1 to indicate 100 Mbit/s operation, 0 for 10 Mbit/s. The value of this pin is reflected on the speed pin.
SAM9G20 RTY: Retry test Must be set to zero for normal operation. If set to one, the back off between collisions is always one slot time. Setting this bit to one helps testing the too many retries condition. Also used in the pause frame tests to reduce the pause counters decrement time from 512 bit times, to every rx_clk cycle. PAE: Pause Enable When set, transmission pauses when a valid pause frame is received.
SAM9G20 35.5.3 Network Status Register Name:EMAC_NSR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 IDLE 1 MDIO 0 – MDIO Returns status of the mdio_in pin. Use the PHY maintenance register for reading managed frames rather than this bit. IDLE 0: The PHY logic is running. 1: The PHY management logic is idle (i.e., has completed). 2017 Microchip Technology Inc.
SAM9G20 35.5.4 Transmit Status Register Name:EMAC_TSR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 UND 5 COMP 4 BEX 3 TGO 2 RLE 1 COL 0 UBR This register, when read, provides details of the status of a transmit. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
SAM9G20 35.5.5 Receive Buffer Queue Pointer Register Name:EMAC_RBQP Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register points to the entry in the receive buffer queue (descriptor list) currently being used. It is written with the start location of the receive buffer descriptor list.
SAM9G20 35.5.6 Transmit Buffer Queue Pointer Register Name:EMAC_TBQP Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 – 0 – ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR This register points to the entry in the transmit buffer queue (descriptor list) currently being used. It is written with the start location of the transmit buffer descriptor list.
SAM9G20 35.5.7 Receive Status Register Name:EMAC_RSR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 OVR 1 REC 0 BNA This register, when read, provides details of the status of a receive. Once read, individual bits may be cleared by writing 1 to them. It is not possible to set a bit to 1 by writing to the register.
SAM9G20 35.5.8 Interrupt Status Register Name:EMAC_ISR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD MFD: Management Frame Done The PHY maintenance register has completed its operation. Cleared on read. RCOMP: Receive Complete A frame has been stored in memory. Cleared on read.
SAM9G20 35.5.9 Interrupt Enable Register Name:EMAC_IER Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD MFD: Management Frame sent Enable management done interrupt. RCOMP: Receive Complete Enable receive complete interrupt. RXUBR: Receive Used Bit Read Enable receive used bit read interrupt.
SAM9G20 35.5.10 Interrupt Disable Register Name:EMAC_IDR Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD MFD: Management Frame sent Disable management done interrupt. RCOMP: Receive Complete Disable receive complete interrupt. RXUBR: Receive Used Bit Read Disable receive used bit read interrupt.
SAM9G20 35.5.11 Interrupt Mask Register Name:EMAC_IMR Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 PTZ 12 PFR 11 HRESP 10 ROVR 9 – 8 – 7 TCOMP 6 TXERR 5 RLE 4 TUND 3 TXUBR 2 RXUBR 1 RCOMP 0 MFD MFD: Management Frame sent Management done interrupt masked. RCOMP: Receive Complete Receive complete interrupt masked. RXUBR: Receive Used Bit Read Receive used bit read interrupt masked.
SAM9G20 35.5.12 PHY Maintenance Register Name:EMAC_MAN Access:Read/Write 31 30 29 SOF 28 27 26 RW 23 PHYA 22 15 14 21 13 25 24 PHYA 20 REGA 19 18 17 16 CODE 12 11 10 9 8 3 2 1 0 DATA 7 6 5 4 DATA DATA For a write operation this is written with the data to be written to the PHY. After a read operation this contains the data read from the PHY. CODE: Must be written to 10. Reads as written. REGA: Register Address Specifies the register in the PHY to access.
SAM9G20 35.5.13 Pause Time Register Name:EMAC_PTR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 PTIME 7 6 5 4 PTIME PTIME: Pause Time Stores the current value of the pause time register which is decremented every 512 bit times. 2017 Microchip Technology Inc.
SAM9G20 35.5.14 Hash Register Bottom Name:EMAC_HRB Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR ADDR: Bits 31:0 of the hash address register. See “Hash Addressing”. DS60001516A-page 626 2017 Microchip Technology Inc.
SAM9G20 35.5.15 Hash Register Top Name:EMAC_HRT Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR ADDR: Bits 63:32 of the hash address register. See “Hash Addressing”. 2017 Microchip Technology Inc.
SAM9G20 35.5.16 Specific Address 1 Bottom Register Name:EMAC_SA1B Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. DS60001516A-page 628 2017 Microchip Technology Inc.
SAM9G20 35.5.17 Specific Address 1 Top Register Name:EMAC_SA1T Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR ADDR The most significant bits of the destination address, that is bits 47 to 32. 2017 Microchip Technology Inc.
SAM9G20 35.5.18 Specific Address 2 Bottom Register Name:EMAC_SA2B Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. DS60001516A-page 630 2017 Microchip Technology Inc.
SAM9G20 35.5.19 Specific Address 2 Top Register Name:EMAC_SA2T Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR ADDR The most significant bits of the destination address, that is bits 47 to 32. 2017 Microchip Technology Inc.
SAM9G20 35.5.20 Specific Address 3 Bottom Register Name:EMAC_SA3B Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. DS60001516A-page 632 2017 Microchip Technology Inc.
SAM9G20 35.5.21 Specific Address 3 Top Register Name:EMAC_SA3T Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR ADDR The most significant bits of the destination address, that is bits 47 to 32. 2017 Microchip Technology Inc.
SAM9G20 35.5.22 Specific Address 4 Bottom Register Name:EMAC_SA4B Access:Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ADDR 23 22 21 20 ADDR 15 14 13 12 ADDR 7 6 5 4 ADDR ADDR Least significant bits of the destination address. Bit zero indicates whether the address is multicast or unicast and corresponds to the least significant bit of the first byte received. DS60001516A-page 634 2017 Microchip Technology Inc.
SAM9G20 35.5.23 Specific Address 4 Top Register Name:EMAC_SA4T Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 ADDR 7 6 5 4 ADDR ADDR The most significant bits of the destination address, that is bits 47 to 32. 2017 Microchip Technology Inc.
SAM9G20 35.5.24 Type ID Checking Register Name:EMAC_TID Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TID 7 6 5 4 TID TID: Type ID checking For use in comparisons with received frames TypeID/Length field. DS60001516A-page 636 2017 Microchip Technology Inc.
SAM9G20 35.5.25 User Input/Output Register Name:EMAC_USRIO Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 CLKEN 0 RMII RMII When set, this bit enables the RMII operation mode. When reset, it selects the MII mode. CLKEN When set, this bit enables the transceiver input clock. Setting this bit to 0 reduces power consumption when the treasurer is not used.
SAM9G20 35.5.26 EMAC Statistic Registers These registers reset to zero on a read and stick at all ones when they count to their maximum value. They should be read frequently enough to prevent loss of data. The receive statistics registers are only incremented when the receive enable bit is set in the network control register. To write to these registers, bit 7 must be set in the network control register. The statistics register block contains the following registers. 35.5.26.
SAM9G20 35.5.26.2 Frames Transmitted OK Register Name:EMAC_FTO Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 FTOK 15 14 13 12 FTOK 7 6 5 4 FTOK FTOK: Frames Transmitted OK A 24-bit register counting the number of frames successfully transmitted, i.e., no underrun and not too many retries. 2017 Microchip Technology Inc.
SAM9G20 35.5.26.3 Single Collision Frames Register Name:EMAC_SCF Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 SCF 7 6 5 4 SCF SCF: Single Collision Frames A 16-bit register counting the number of frames experiencing a single collision before being successfully transmitted, i.e., no underrun. DS60001516A-page 640 2017 Microchip Technology Inc.
SAM9G20 35.5.26.4 Multicollision Frames Register Name:EMAC_MCF Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 MCF 7 6 5 4 MCF MCF: Multicollision Frames A 16-bit register counting the number of frames experiencing between two and fifteen collisions prior to being successfully transmitted, i.e., no underrun and not too many retries. 2017 Microchip Technology Inc.
SAM9G20 35.5.26.5 Frames Received OK Register Name:EMAC_FRO Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 FROK 15 14 13 12 FROK 7 6 5 4 FROK FROK: Frames Received OK A 24-bit register counting the number of good frames received, i.e., address recognized and successfully copied to memory.
SAM9G20 35.5.26.6 Frames Check Sequence Errors Register Name:EMAC_FCSE Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 FCSE FCSE: Frame Check Sequence Errors An 8-bit register counting frames that are an integral number of bytes, have bad CRC and are between 64 and 1518 bytes in length (1536 if bit 8 set in network configuration register).
SAM9G20 35.5.26.
SAM9G20 35.5.26.8 Deferred Transmission Frames Register Name:EMAC_DTF Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 DTF 7 6 5 4 DTF DTF: Deferred Transmission Frames A 16-bit register counting the number of frames experiencing deferral due to carrier sense being active on their first attempt at transmission.
SAM9G20 35.5.26.9 Late Collisions Register Name:EMAC_LCOL Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 LCOL LCOL: Late Collisions An 8-bit register counting the number of frames that experience a collision after the slot time (512 bits) has expired. A late collision is counted twice; i.e., both as a collision and a late collision.
SAM9G20 35.5.26.10 Excessive Collisions Register Name:EMAC_ECOL Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 EXCOL EXCOL: Excessive Collisions An 8-bit register counting the number of frames that failed to be transmitted because they experienced 16 collisions. 2017 Microchip Technology Inc.
SAM9G20 35.5.26.11 Transmit Underrun Errors Register Name:EMAC_TUND Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TUND TUND: Transmit Underruns An 8-bit register counting the number of frames not transmitted due to a transmit DMA underrun. If this register is incremented, then no other statistics register is incremented.
SAM9G20 35.5.26.12 Carrier Sense Errors Register Name:EMAC_CSE Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 CSE CSE: Carrier Sense Errors An 8-bit register counting the number of frames transmitted where carrier sense was not seen during transmission or where carrier sense was deasserted after being asserted in a transmit frame without collision (no underrun).
SAM9G20 35.5.26.13 Receive Resource Errors Register Name:EMAC_RRE Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RRE 7 6 5 4 RRE RRE: Receive Resource Errors A 16-bit register counting the number of frames that were address matched but could not be copied to memory because no receive buffer was available. DS60001516A-page 650 2017 Microchip Technology Inc.
SAM9G20 35.5.26.14 Receive Overrun Errors Register Name:EMAC_ROV Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 ROVR ROVR: Receive Overrun An 8-bit register counting the number of frames that are address recognized but were not copied to memory due to a receive DMA overrun. 2017 Microchip Technology Inc.
SAM9G20 35.5.26.15 Receive Symbol Errors Register Name:EMAC_RSE Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RSE RSE: Receive Symbol Errors An 8-bit register counting the number of frames that had rx_er asserted during reception.
SAM9G20 35.5.26.16 Excessive Length Errors Register Name:EMAC_ELE Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 EXL EXL: Excessive Length Errors An 8-bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length but do not have either a CRC error, an alignment error nor a receive symbol error.
SAM9G20 35.5.26.17 Receive Jabbers Register Name:EMAC_RJA Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RJB RJB: Receive Jabbers An 8-bit register counting the number of frames received exceeding 1518 bytes (1536 if bit 8 set in network configuration register) in length and have either a CRC error, an alignment error or a receive symbol error.
SAM9G20 35.5.26.18 Undersize Frames Register Name:EMAC_USF Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 USF USF: Undersize frames An 8-bit register counting the number of frames received less than 64 bytes in length but do not have either a CRC error, an alignment error or a receive symbol error. 2017 Microchip Technology Inc.
SAM9G20 35.5.26.19 SQE Test Errors Register Name:EMAC_STE Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 SQER SQER: SQE test errors An 8-bit register counting the number of frames where col was not asserted within 96 bit times (an interframe gap) of tx_en being deasserted in half duplex mode. DS60001516A-page 656 2017 Microchip Technology Inc.
SAM9G20 35.5.26.20 Received Length Field Mismatch Register Name:EMAC_RLE Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RLFM RLFM: Receive Length Field Mismatch An 8-bit register counting the number of frames received that have a measured length shorter than that extracted from its length field. Checking is enabled through bit 16 of the network configuration register.
SAM9G20 36. USB Device Port (UDP) 36.1 Overview The USB Device Port (UDP) is compliant with the Universal Serial Bus (USB) V2.0 full-speed device specification. Each endpoint can be configured in one of several USB transfer types. It can be associated with one or two banks of a dual-port RAM used to store the current data payload. If two banks are used, one DPR bank is read or written by the processor, while the other is read or written by the USB device peripheral.
SAM9G20 A USB 2.0 full-speed pad is embedded and controlled by the Serial Interface Engine (SIE). The signal external_resume is optional. It allows the UDP peripheral to wake up once in system mode. The host is then notified that the device asks for a resume. This optional feature must be also negotiated with the host during the enumeration. 36.3 Product Dependencies For further details on the USB Device hardware implementation, see the specific Product Properties document.
SAM9G20 36.4.2 VBUS Monitoring VBUS monitoring is required to detect host connection. VBUS monitoring is done using a standard PIO with internal pullup disabled. When the host is switched off, it should be considered as a disconnect, the pullup must be disabled in order to prevent powering the host through the pull-up resistor. When the host is disconnected and the transceiver is enabled, then DDP and DDM are floating. This may lead to over consumption.
SAM9G20 36.5.1.1 USB V2.0 Full-speed Transfer Types A communication flow is carried over one of four transfer types defined by the USB device.
SAM9G20 Figure 36-4: Control Read and Write Sequences Setup Stage Control Read Setup TX Setup Stage Control Write No Data Control Setup TX Data Stage Data OUT TX Status Stage Data OUT TX Data Stage Data IN TX Setup Stage Status Stage Setup TX Status IN TX Data IN TX Status IN TX Status Stage Status OUT TX Note 1: During the Status IN stage, the host waits for a zero length packet (Data IN transaction with no data) from the device using DATA1 PID.
SAM9G20 Figure 36-5: Setup Transaction Followed by a Data OUT Transaction Setup Received USB Bus Packets Setup PID Setup Handled by Firmware ACK PID Data Setup RXSETUP Flag Data OUT PID Data OUT Data OUT PID Data OUT ACK PID Cleared by Firmware Set by USB Device Peripheral RX_Data_BKO (UDP_CSRx) 36.5.2.
SAM9G20 Figure 36-6: Data IN Transfer for Non Ping-pong Endpoint Prevous Data IN TX USB Bus Packets Data IN PID Microcontroller Load Data in FIFO Data IN 1 ACK PID Data IN PID NAK PID Data is Sent on USB Bus Data IN PID Data IN 2 ACK PID TXPKTRDY Flag (UDP_CSRx) Set by the firmware Cleared by Hw Cleared by Hw Set by the firmware Interrupt Pending Interrupt Pending TXCOMP Flag (UDP_CSRx) Payload in FIFO Cleared by Firmware DPR access by the firmware FIFO (DPR) Content Data IN 1 Cleared
SAM9G20 5. 6. 7. writing zero or more byte values in the endpoint’s UDP_FDRx register. The microcontroller is notified that the first Bank has been released by the USB device when TXCOMP in the endpoint’s UDP_CSRx register is set. An interrupt is pending while TXCOMP is being set. Once the microcontroller has received TXCOMP for the first Bank, it notifies the USB device that it has prepared the second Bank to be sent, raising TXPKTRDY in the endpoint’s UDP_CSRx register.
SAM9G20 Figure 36-9: USB Bus Packets Data OUT Transfer for Non Ping-pong Endpoints Host Sends Data Payload Microcontroller Transfers Data Host Sends the Next Data Payload Data OUT PID ACK PID Data OUT 1 RX_DATA_BK0 (UDP_CSRx) Data OUT2 PID Data OUT2 Host Resends the Next Data Payload NAK PID Data OUT PID Data OUT2 ACK PID Interrupt Pending Cleared by Firmware, Data Payload Written in FIFO Set by USB Device FIFO (DPR) Content Data OUT 1 Written by USB Device Data OUT 1 Data OUT 2 Microcon
SAM9G20 6. The microcontroller transfers out data received from the endpoint’s memory to the microcontroller’s memory. Data received is made available by reading the endpoint’s UDP_FDRx register. 7. The microcontroller notifies the USB peripheral device that it has finished the transfer by clearing RX_DATA_BK0 in the endpoint’s UDP_CSRx register. 8. A third Data OUT packet can be accepted by the USB peripheral device and copied in the FIFO Bank 0. 9.
SAM9G20 The following procedure generates a stall packet: 1. 2. 3. The microcontroller sets the FORCESTALL flag in the UDP_CSRx endpoint’s register. The host receives the stall packet. The microcontroller is notified that the device has sent the stall by polling the STALLSENT to be set. An endpoint interrupt is pending while STALLSENT is set. The microcontroller must clear STALLSENT to clear the interrupt.
SAM9G20 • TXPKTRDY has already been set: - Clear TXPKTRDY and read it back until actually read at 0. - Set TXPKTRDY and read it back until actually read at 1. - Clear TXPKTRDY so that no packet is ready to be sent. - Reset the endpoint to clear the FIFO (pointers). (See Section 36.6.9 ”UDP Reset Endpoint Register”.) 36.5.3 Controlling Device States A USB device has several possible states. Refer to Chapter 9 of the Universal Serial Bus Specification, Rev 2.0.
SAM9G20 36.5.3.1 Not Powered State Self powered devices can detect 5V VBUS using a PIO as described in the typical connection section. When the device is not connected to a host, device power consumption can be reduced by disabling MCK for the UDP, disabling UDPCK and disabling the transceiver. DDP and DDM lines are pulled down by 330 KΩ resistors. 36.5.3.
SAM9G20 36.5.3.8 Sending a Device Remote Wakeup In Suspend state it is possible to wake up the host sending an external resume. • The device must wait at least 5 ms after being entered in suspend before sending an external resume. • The device has 10 ms from the moment it starts to drain current and it forces a K state to resume the host. • The device must force a K state from 1 to 15 ms to resume the host To force a K state to the bus (DM at 3.
SAM9G20 36.6 USB Device (UDP) User Interface WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers, including the UDP_TXVC register.
SAM9G20 36.6.1 UDP Frame Number Register Name:UDP_FRM_NUM Access:Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 FRM_OK 16 FRM_ERR 15 – 14 – 13 – 12 – 11 – 10 9 FRM_NUM 8 7 6 5 4 3 2 1 0 FRM_NUM FRM_NUM[10:0]: Frame Number as Defined in the Packet Field Formats This 11-bit value is incremented by the host on a per frame basis. This value is updated at each start of frame. Value Updated at the SOF_EOP (Start of Frame End of Packet).
SAM9G20 36.6.2 UDP Global State Register Name:UDP_GLB_STAT Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 – 6 – 5 – 4 – 3 RSMINPR 2 – 1 CONFG 0 FADDEN This register is used to get and set the device state as specified in Chapter 9 of the USB Serial Bus Specification, Rev.2.0. FADDEN: Function Address Enable Read: 0: Device is not in address state. 1: Device is in address state.
SAM9G20 36.6.3 UDP Function Address Register Name:UDP_FADDR Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – FEN 7 – 6 5 4 3 FADD 2 1 0 FADD[6:0]: Function Address Value The Function Address Value must be programmed by firmware once the device receives a set address request from the host, and has achieved the status stage of the no-data control sequence.
SAM9G20 36.6.
SAM9G20 36.6.
SAM9G20 36.6.
SAM9G20 36.6.
SAM9G20 SOFINT: Start of Frame Interrupt Status 0: No Start of Frame Interrupt pending. 1: Start of Frame Interrupt has been raised. This interrupt is raised each time a SOF token has been detected. It can be used as a synchronization signal by using isochronous endpoints. ENDBUSRES: End of BUS Reset Interrupt Status 0: No End of Bus Reset Interrupt pending. 1: End of Bus Reset Interrupt has been raised. This interrupt is raised at the end of a UDP reset sequence.
SAM9G20 36.6.8 UDP Interrupt Clear Register Name:UDP_ICR Access:Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 WAKEUP 12 ENDBUSRES 11 SOFINT 10 EXTRSM 9 RXRSM 8 RXSUSP 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – RXSUSP: Clear UDP Suspend Interrupt 0: No effect. 1: Clears UDP Suspend Interrupt. RXRSM: Clear UDP Resume Interrupt 0: No effect. 1: Clears UDP Resume Interrupt. EXTRSM: Clear UDP External Resume Interrupt 0: No effect.
SAM9G20 36.6.
SAM9G20 36.6.10 UDP Endpoint Control and Status Register Name:UDP_CSRx [x = 0..
SAM9G20 RX_DATA_BK0: Receive Data Bank 0 This flag generates an interrupt while it is set to one. Write (Cleared by the firmware): 0: Notify USB peripheral device that data have been read in the FIFO's Bank 0. 1: To leave the read value unchanged. Read (Set by the USB peripheral): 0: No data packet has been received in the FIFO's Bank 0. 1: A data packet has been received, it has been stored in the FIFO's Bank 0.
SAM9G20 TXPKTRDY: Transmit Packet Ready This flag is cleared by the USB device. This flag is set by the USB device firmware. Read: 0: There is no data to send. 1: The data is waiting to be sent upon reception of token IN. Write: 0: Can be used in the procedure to cancel transmission data. (See Section 36.5.2.5 ”Transmit Data Cancellation”) 1: A new data payload has been written in the FIFO by the firmware and is ready to be sent. This flag is used to generate a Data IN transaction (device to host).
SAM9G20 EPTYPE[2:0]: Endpoint Type Read/Write 000 Control 001 Isochronous OUT 101 Isochronous IN 010 Bulk OUT 110 Bulk IN 011 Interrupt OUT 111 Interrupt IN DTGLE: Data Toggle Read-only 0: Identifies DATA0 packet. 1: Identifies DATA1 packet. Refer to Chapter 8 of the Universal Serial Bus Specification, Rev. 2.0 for more information on DATA0, DATA1 packet definitions. EPEDS: Endpoint Enable Disable Read: 0: Endpoint disabled. 1: Endpoint enabled. Write: 0: Disables endpoint.
SAM9G20 36.6.11 UDP FIFO Data Register Name:UDP_FDRx [x = 0..5] Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – – 7 6 5 4 3 2 1 0 FIFO_DATA FIFO_DATA[7:0]: FIFO Data Value The microcontroller can push or pop values in the FIFO through this register. RXBYTECNT in the corresponding UDP_CSRx register is the number of bytes to be read from the FIFO (sent by the host).
SAM9G20 36.6.12 UDP Transceiver Control Register Name:UDP_TXVC Access:Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 PUON TXVDIS 7 – 6 – 5 – 4 – 3 – 2 – 1 0 – – WARNING: The UDP peripheral clock in the Power Management Controller (PMC) must be enabled before any read/write operations to the UDP registers including the UDP_TXVC register.
SAM9G20 37. USB Host Port (UHP) 37.1 Overview The USB Host Port (UHP) interfaces the USB with the host application. It handles Open HCI protocol (Open Host Controller Interface) as well as USB v2.0 Full-speed and Low-speed protocols. The USB Host Port integrates a root hub and transceivers on downstream ports. It provides several high-speed half-duplex serial communication ports at a baud rate of 12 Mbit/s. Up to 127 USB devices (printer, camera, mouse, keyboard, disk, etc.
SAM9G20 37.3 37.3.1 Product Dependencies I/O Lines DPs and DMs are not controlled by any PIO controllers. The embedded USB physical transceivers are controlled by the USB host controller. 37.3.2 Power Management The USB host controller requires a 48 MHz clock. This clock must be generated by a PLL with a correct accuracy of ± 0.25%.
SAM9G20 Figure 37-2: USB Host Communication Channels Device Enumeration Open HCI Operational Registers Host Controller Communications Area Mode Interrupt 0 HCCA Interrupt 1 Status Interrupt 2 ... Event Interrupt 31 Frame Int ... Ratio Control Bulk ... Done Device Register in Memory Space Shared RAM = Transfer Descriptor 37.4.
SAM9G20 37.5 Typical Connection Figure 37-4: Board Schematic to Interface UHP Device Controller 5V 0.20A Type A Connector 10μF HDMA or HDMB HDPA or HDPB 100nF 10nF REXT REXT A termination serial resistor must be connected to HDP and HDM. The resistor value is defined in the electrical specification of the product (REXT). DS60001516A-page 692 2017 Microchip Technology Inc.
SAM9G20 38. Image Sensor Interface (ISI) 38.1 Overview The Image Sensor Interface (ISI) connects a CMOS-type image sensor to the processor and provides image capture in various formats. It does data conversion, if necessary, before the storage in memory through DMA. The ISI supports color CMOS image sensor and grayscale image sensors with a reduced set of functionalities. In grayscale mode, the data stream is stored in memory without any processing and so is not compatible with the LCD controller.
SAM9G20 Block Diagram Hsync/Len Vsync/Fen Image Sensor Interface Block Diagram Timing Signals Interface CCIR-656 Embedded Timing Decoder(SAV/EAV) CMOS sensor Pixel input up to 12 bit YCbCr 4:2:2 8:8:8 RGB 5:6:5 Camera Interrupt Request Line From Rx buffers Pixel Clock Domain APB Interface APB Clock Domain AHB Clock Domain Frame Rate Clipping + Color Conversion YCC to RGB Pixel Sampling Module 2-D Image Scaler Clipping + Color Conversion RGB to YCC CMOS sensor pixel clock input 38.
SAM9G20 Figure 38-3: HSYNC and VSYNC Synchronization Frame ISI_VSYNC 1 line ISI_HSYNC ISI_PCK DATA[7..0] Figure 38-4: Y Cb Y Cr Y Cb Y Cr Y Cb Y Cr SAV and EAV Sequence Synchronization ISII_PCK DATA[7..0] 38.3.2 FF 00 00 SAV 80 Y Cb Y Cr Y Cb Y Cr Active Video Y Y Cr Y Cb FF 00 00 EAV 9D Data Ordering The RGB color space format is required for viewing images on a display screen preview, and the YCbCr color space format is required for encoding.
SAM9G20 Table 38-3: RGB Format in Default Mode, RGB_CFG = 00, No Swap Byte 0 R4(i) R3(i) R2(i) R1(i) R0(i) G5(i) G4(i) G3(i) Byte 1 G2(i) G1(i) G0(i) B4(i) B3(i) B2(i) B1(i) B0(i) Byte 2 R4(i+1) R3(i+1) R2(i+1) R1(i+1) R0(i+1) G5(i+1) G4(i+1) G3(i+1) Byte 3 G2(i+1) G1(i+1) G0(i+1) B4(i+1) B3(i+1) B2(i+1) B1(i+1) B0(i+1) RGB 5:6:5 Table 38-4: Mode RGB Format, RGB_CFG = 10 (Mode 2), No Swap Byte D7 D6 D5 D4 D3 D2 D1 D0 Byte 0 G2(i) G1(i) G0(i) R4(i) R3(i)
SAM9G20 Table 38-6: Decimation Factor Dec value 0->15 16 17 18 19 ... 124 125 126 127 Dec Factor X 1 1.063 1.125 1.188 ... 7.750 7.813 7.875 7.
SAM9G20 38.3.4.2 Color Space Conversion This module converts YCrCb or YUV pixels to RGB color space. Clipping is performed to ensure that the samples value do not exceed the allowable range. The conversion matrix is defined below and is fully programmable: Y – Y off C0 0 C1 R G = C 0 – C 2 – C 3 × C b – C boff B C0 C4 0 C r – C roff Example of programmable value to convert YCrCb to RGB: R = 1.164 ⋅ ( Y – 16 ) + 1.596 ⋅ ( C r – 128 ) G = 1.164 ⋅ ( Y – 16 ) – 0.813 ⋅ ( C r – 128 ) – 0.
SAM9G20 Example The first FBD, stored at address 0x30000, defines the location of the first frame buffer. Destination Address: frame buffer ID0 0x02A000 Next FBD address: 0x30010 Second FBD, stored at address 0x30010, defines the location of the second frame buffer. Destination Address: frame buffer ID1 0x3A000 Transfer width: 32 bit Next FBD address: 0x30000, wrapping to first FBD. Using this technique, several frame buffers can be configured through the linked list.
SAM9G20 38.3.5 38.3.5.1 Codec Path Color Space Conversion Depending on user selection, this module can be bypassed so that input YCrCb stream is directly connected to the format converter module. If the RGB input stream is selected, this module converts RGB to YCrCb color space with the formulas given below: Y Cr = C0 C1 C2 Cb –C6 –C7 C8 C3 –C4 –C5 Y off R × G + Cr off B Cb off An example of coefficients is given below: Y = 0.257 ⋅ R + 0.504 ⋅ G + 0.098 ⋅ B + 16 C = 0.439 ⋅ R – 0.368 ⋅ G – 0.
SAM9G20 38.
SAM9G20 38.4.1 ISI Control 1 Register Name: ISI_CR1 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 SFD 23 22 21 20 SLD 15 CODEC_ON 14 7 CRC_SYNC 6 EMB_SYNC 13 12 FULL 11 – 10 9 FRATE 8 5 – 4 PIXCLK_POL 3 VSYNC_POL 2 HSYNC_POL 1 ISI_DIS 0 ISI_RST THMASK ISI_RST: Image Sensor Interface Reset Write-only. Refer to bit SOFTRST in “ISI Status Register” for soft reset status. 0: No action 1: Resets the image sensor interface.
SAM9G20 THMASK: Threshold Mask 0: 4, 8 and 16 AHB bursts are allowed 1: 8 and 16 AHB bursts are allowed 2: Only 16 AHB bursts are allowed CODEC_ON: Enable the Codec Path Enable Bit Write-only. 0: The codec path is disabled 1: The codec path is enabled and the next frame is captured. Refer to bit CDC_PND in “ISI Status Register” . SLD: Start of Line Delay SLD pixel clock periods to wait before the beginning of a line. SFD: Start of Frame Delay SFD lines are skipped at the beginning of the frame.
SAM9G20 38.4.2 ISI Control 2 Register Name: ISI_CR2 Access: Read/Write 31 30 29 RGB_CFG 23 28 YCC_SWAP 22 21 20 27 – 26 25 IM_HSIZE 24 19 18 17 16 IM_HSIZE 15 COL_SPACE 14 RGB_SWAP 13 GRAYSCALE 12 RGB_MODE 11 GS_MODE 10 9 IM_VSIZE 8 7 6 5 4 3 2 1 0 IM_VSIZE IM_VSIZE: Vertical Size of the Image Sensor [0..
SAM9G20 RGB_CFG: Defines RGB Pattern when RGB_MODE is set to 1 RGB_CFG Byte 0 Byte 1 Byte 2 Byte 3 00: Default R/G(MSB) G(LSB)/B R/G(MSB) G(LSB)/B 01: Mode1 B/G(MSB) G(LSB)/R B/G(MSB) G(LSB)/R 10: Mode2 G(LSB)/R B/G(MSB) G(LSB)/R B/G(MSB) 11: Mode3 G(LSB)/B R/G(MSB) G(LSB)/B R/G(MSB) If RGB_MODE is set to RGB 8:8:8, then RGB_CFG = 0 implies RGB color sequence, else it implies BGR color sequence. 2017 Microchip Technology Inc.
SAM9G20 38.4.3 ISI Status Register Name: ISI_SR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 FR_OVR 8 FO_C_EMP 7 FO_P_EMP 6 FO_P_OVF 5 FO_C_OVF 4 CRC_ERR 3 CDC_PND 2 SOFTRST 1 DIS 0 SOF SOF: Start of Frame 0: No start of frame has been detected. 1: A start of frame has been detected. DIS: Image Sensor Interface Disable 0: The image sensor interface is enabled.
SAM9G20 FO_C_EMP 0: The DMA has not finished transferring all the contents of the codec FIFO. 1: The DMA has finished transferring all the contents of the codec FIFO. FR_OVR: Frame Rate Overrun 0: No frame overrun. 1: Frame overrun, the current frame is being skipped because a vsync signal has been detected while flushing FIFOs. 2017 Microchip Technology Inc.
SAM9G20 38.4.4 Interrupt Enable Register Name: ISI_IER Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 FR_OVR 8 FO_C_EMP 7 FO_P_EMP 6 FO_P_OVF 5 FO_C_OVF 4 CRC_ERR 3 – 2 SOFTRST 1 DIS 0 SOF SOF: Start of Frame 1: Enables the Start of Frame interrupt. DIS: Image Sensor Interface Disable 1: Enables the DIS interrupt. SOFTRST: Soft Reset 1: Enables the Soft Reset Completion interrupt.
SAM9G20 38.4.5 ISI Interrupt Disable Register Name: ISI_IDR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 FR_OVR 8 FO_C_EMP 7 FO_P_EMP 6 FO_P_OVF 5 FO_C_OVF 4 CRC_ERR 3 – 2 SOFTRST 1 DIS 0 SOF SOF: Start of Frame 1: Disables the Start of Frame interrupt. DIS: Image Sensor Interface Disable 1: Disables the DIS interrupt. SOFTRST 1: Disables the soft reset completion interrupt.
SAM9G20 38.4.6 ISI Interrupt Mask Register Name: ISI_IMR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 FR_OVR 8 FO_C_EMP 7 FO_P_EMP 6 FO_P_OVF 5 FO_C_OVF 4 CRC_ERR 3 – 2 SOFTRST 1 DIS 0 SOF SOF: Start of Frame 0: The Start of Frame interrupt is disabled. 1: The Start of Frame interrupt is enabled. DIS: Image Sensor Interface Disable 0: The DIS interrupt is disabled.
SAM9G20 38.4.7 ISI Preview Register Name: ISI_PSIZE Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 19 18 17 24 PREV_HSIZE 16 PREV_HSIZE 15 – 14 – 13 – 12 – 11 – 10 – 9 7 6 5 4 3 2 1 8 PREV_VSIZE 0 PREV_VSIZE PREV_VSIZE: Vertical Size for the Preview Path Vertical Preview size = PREV_VSIZE + 1 (480 max only in RGB mode). PREV_HSIZE: Horizontal Size for the Preview Path Horizontal Preview size = PREV_HSIZE + 1 (640 max only in RGB mode).
SAM9G20 38.4.8 ISI Preview Decimation Factor Register Name: ISI_PDECF Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 DEC_FACTOR DEC_FACTOR: Decimation Factor DEC_FACTOR is 8-bit width, range is from 16 to 255. Values from 0 to 16 do not perform any decimation. DS60001516A-page 712 2017 Microchip Technology Inc.
SAM9G20 38.4.9 ISI Preview Primary FBD Register Name: ISI_PPFBD Access: Read/Write 31 30 29 28 27 PREV_FBD_ADDR 26 25 24 23 22 21 20 19 PREV_FBD_ADDR 18 17 16 15 14 13 12 11 PREV_FBD_ADDR 10 9 8 7 6 5 4 3 PREV_FBD_ADDR 2 1 0 PREV_FBD_ADDR: Base Address for Preview Frame Buffer Descriptor Written with the address of the start of the preview frame buffer queue, reads as a pointer to the current buffer being used. The frame buffer is forced to word alignment.
SAM9G20 38.4.10 ISI Codec DMA Base Address Register Name: ISI_CDBA Access: Read/Write 31 30 29 28 27 CODEC_DMA_ADDR 26 25 24 23 22 21 20 19 CODEC_DMA_ADDR 18 17 16 15 14 13 12 11 CODEC_DMA_ADDR 10 9 8 7 6 5 4 3 CODEC_DMA_ADDR 2 1 0 CODEC_DMA_ADDR: Base Address for Codec DMA This register contains codec datapath start address of buffer location. DS60001516A-page 714 2017 Microchip Technology Inc.
SAM9G20 38.4.11 ISI Color Space Conversion YCrCb to RGB Set 0 Register Name: ISI_Y2R_SET0 Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 C3 23 22 21 20 C2 15 14 13 12 C1 7 6 5 4 C0 C0: Color Space Conversion Matrix Coefficient C0 C0 element, default step is 1/128, ranges from 0 to 1.9921875. C1: Color Space Conversion Matrix Coefficient C1 C1 element, default step is 1/128, ranges from 0 to 1.9921875.
SAM9G20 38.4.12 ISI Color Space Conversion YCrCb to RGB Set 1 Register Name: ISI_Y2R_SET1 Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 Cboff 13 Croff 12 Yoff 11 – 10 – 9 – 8 C4 C4 C4: Color Space Conversion Matrix Coefficient C4 C4 element default step is 1/128, ranges from 0 to 3.9921875. Yoff: Color Space Conversion Luminance Default Offset 0: No offset. 1: Offset = 128.
SAM9G20 38.4.13 ISI Color Space Conversion RGB to YCrCb Set 0 Register Name: ISI_R2Y_SET0 Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 Roff 19 18 17 16 11 10 9 8 3 2 1 0 C2 15 14 13 12 C1 7 6 5 4 C0 C0: Color Space Conversion Matrix Coefficient C0 C0 element default step is 1/256, from 0 to 0.49609375. C1: Color Space Conversion Matrix Coefficient C1 C1 element default step is 1/128, from 0 to 0.9921875.
SAM9G20 38.4.14 ISI Color Space Conversion RGB to YCrCb Set 1 Register Name: ISI_R2Y_SET1 Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 Goff 19 18 17 16 11 10 9 8 3 2 1 0 C5 15 14 13 12 C4 7 6 5 4 C3 C3: Color Space Conversion Matrix Coefficient C3 C0 element default step is 1/128, ranges from 0 to 0.9921875. C4: Color Space Conversion Matrix Coefficient C4 C1 element default step is 1/256, ranges from 0 to 0.49609375.
SAM9G20 38.4.15 ISI Color Space Conversion RGB to YCrCb Set 2 Register Name: ISI_R2Y_SET2 Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 Boff 19 18 17 16 11 10 9 8 3 2 1 0 C8 15 14 13 12 C7 7 6 5 4 C6 C6: Color Space Conversion Matrix Coefficient C6 C6 element default step is 1/512, ranges from 0 to 0.2480468875. C7: Color Space Conversion Matrix coefficient C7 C7 element default step is 1/256, ranges from 0 to 0.49609375.
SAM9G20 39. Analog-to-Digital Converter (ADC) 39.1 Overview The ADC is based on a Successive Approximation Register (SAR) 10-bit Analog-to-Digital Converter (ADC). It also integrates a 4-to-1 analog multiplexer, making possible the analog-to-digital conversions of 4 analog lines. The conversions extend from 0V to ADVREF. The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register.
SAM9G20 39.3 Signal Description Table 39-1: ADC Pin Description Pin Name Description VDDANA Analog power supply ADVREF Reference voltage AD0–AD3 Analog input channels ADTRG External trigger 39.4 39.4.1 Product Dependencies Power Management The ADC is automatically clocked after the first conversion in Normal Mode. In Sleep Mode, the ADC clock is automatically stopped after each conversion.
SAM9G20 39.5.3 Conversion Resolution The ADC supports 8-bit or 10-bit resolutions. The 8-bit selection is performed by setting the bit LOWRES in the ADC Mode Register (ADC_MR). By default, after a reset, the resolution is the highest and the DATA field in the data registers is fully used. By setting the bit LOWRES, the ADC switches in the lowest resolution and the conversion results can be read in the eight lowest significant bits of the data registers.
SAM9G20 Figure 39-3: GOVRE and OVREx Flag Behavior Read ADC_SR ADTRG CH0 (ADC_CHSR) CH1 (ADC_CHSR) ADC_LCDR Undefined Data ADC_CDR0 Undefined Data ADC_CDR1 EOC0 (ADC_SR) EOC1 (ADC_SR) Data B Data A Data C Data A Data C Undefined Data Data B Conversion Conversion Conversion Read ADC_CDR0 Read ADC_CDR1 GOVRE (ADC_SR) DRDY (ADC_SR) OVRE0 (ADC_SR) Warning: If the corresponding channel is disabled during a conversion or if it is disabled and then reenabled during a conversion, its associate
SAM9G20 39.5.5 Conversion Triggers Conversions of the active analog channels are started with a software or a hardware trigger. The software trigger is provided by writing the Control Register (ADC_CR) with the bit START at 1. The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the external trigger input of the ADC (ADTRG). The hardware trigger is selected with the field TRGSEL in the Mode Register (ADC_MR).
SAM9G20 39.
SAM9G20 39.6.1 ADC Control Register Name:ADC_CR Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – START SWRST SWRST: Software Reset 0: No effect. 1: Resets the ADC simulating a hardware reset. START: Start Conversion 0: No effect. 1: Begins analog-to-digital conversion. DS60001516A-page 726 2017 Microchip Technology Inc.
SAM9G20 39.6.2 ADC Mode Register Name:ADC_MR Access: Read/Write 31 30 29 28 – – – – 23 22 21 20 – – – 15 14 13 – – 27 26 25 24 17 16 10 9 8 2 1 SHTIM 19 18 STARTUP 12 11 PRESCAL 7 6 5 4 – – SLEEP LOWRES 3 TRGSEL 0 TRGEN TRGEN: Trigger Enable TRGEN Selected TRGEN 0 Hardware triggers are disabled. Starting a conversion is only possible by software. 1 Hardware trigger selected by TRGSEL field is enabled.
SAM9G20 STARTUP: Start Up Time Startup Time = (STARTUP+1) * 8 / ADCClock SHTIM: Sample & Hold Time Sample & Hold Time = (SHTIM+1) / ADCClock DS60001516A-page 728 2017 Microchip Technology Inc.
SAM9G20 39.6.3 ADC Channel Enable Register Name:ADC_CHER Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – CH3 CH2 CH1 CH0 CHx: Channel x Enable 0: No effect. 1: Enables the corresponding channel. 2017 Microchip Technology Inc.
SAM9G20 39.6.4 ADC Channel Disable Register Name:ADC_CHDR Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – CH3 CH2 CH1 CH0 CHx: Channel x Disable 0: No effect. 1: Disables the corresponding channel.
SAM9G20 39.6.5 ADC Channel Status Register Name:ADC_CHSR Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – CH3 CH2 CH1 CH0 CHx: Channel x Status 0: Corresponding channel is disabled. 1: Corresponding channel is enabled. 2017 Microchip Technology Inc.
SAM9G20 39.6.6 ADC Status Register Name:ADC_SR Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – RXBUFF ENDRX GOVRE DRDY 15 14 13 12 11 10 9 8 – – – – OVRE3 OVRE2 OVRE1 OVRE0 7 6 5 4 3 2 1 0 – – – – EOC3 EOC2 EOC1 EOC0 EOCx: End of Conversion x 0: Corresponding analog channel is disabled, or the conversion is not finished. 1: Corresponding analog channel is enabled and conversion is complete.
SAM9G20 39.6.7 ADC Last Converted Data Register Name:ADC_LCDR Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 – – – – – – 7 6 5 4 3 2 8 LDATA 1 0 LDATA LDATA: Last Data Converted The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed. 2017 Microchip Technology Inc.
SAM9G20 39.6.
SAM9G20 39.6.
SAM9G20 39.6.
SAM9G20 39.6.11 ADC Channel Data Register Name:ADC_CDRx Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 – – – – – – 7 6 5 4 3 2 8 DATA 1 0 DATA DATA: Converted Data The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion is completed.
SAM9G20 40. Electrical Characteristics 40.1 Absolute Maximum Ratings Table 40-1: Absolute Maximum Ratings* Operating Temperature (Industrial)................-40°C to + 85°C Junction Temperature.................................................+125°C Storage Temperature...................................-40°C to + 150°C Voltage on Input Pins with Respect to Ground .....-0.3V to VDDIO+0.
SAM9G20 40.2 DC Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C, unless otherwise specified. Table 40-2: DC Characteristics Symbol Parameter VVDDCOR Conditions Min Typ Max Unit DC Supply Core 0.9 1.0 1.1 V VVDDBU DC Supply Backup 0.9 1.0 1.1 V VVDDPLL DC Supply PLL 0.9 1.0 1.1 V 1.65 – 3.6 V 1.65/3.0 1.8/3.3 1.95/3.6 V 1.65 – 3.6 V VVDDANA DC Supply Analog 3.0 3.3 3.
SAM9G20 40.3 Power Consumption • Typical power consumption of PLLs, Slow Clock and Main Oscillator • Power consumption of power supply in four different modes: Active, Idle, Ultra Low-power and Backup • Power consumption by peripheral: calculated as the difference in current measurement after having enabled then disabled the corresponding clock 40.3.
SAM9G20 Table 40-4: Power Consumption by Peripheral in Active Mode Peripheral Consumption PIO Controller 2.5 USART 7.0 UHP 5.4 UDP 4.9 ADC 4.1 TWI 4.6 SPI 4.0 MCI 6.4 SSC 7.0 Timer Counter Channels 1.8 ISI 4.6 EMAC 34.6 Unit µA/MHz 40.4 Clock Characteristics 40.4.1 Processor Clock Characteristics Table 40-5: Processor Clock Waveform Parameters Symbol Parameter 1/(tCPPCK) Processor Clock Frequency 40.4.2 Conditions VVDDCORE = 0.
SAM9G20 40.4.3 XIN Clock Characteristics Table 40-7: XIN Clock Electrical Characteristics Symbol Parameter 1/ (tCPXIN) Min Max Unit XIN Clock Frequency – 50 MHz tCPXIN XIN Clock Period 20 – ns tCHXIN XIN Clock High Half-period 0.4 × tCPXIN 0.6 × tCPXIN ns tCLXIN XIN Clock Low Half-period 0.4 × tCPXIN 0.6 × tCPXIN ns CIN XIN Input Capacitance – 25 pF RIN XIN Pull-down Resistor – 1000 kΩ VIN XIN Voltage VDDOSC VDDOSC V 40.4.
SAM9G20 40.5 Crystal Oscillator Characteristics The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C and worst case of power supply, unless otherwise specified. 40.5.1 32 kHz Oscillator Characteristics Table 40-10: 32 kHz Oscillator Characteristics Symbol Parameter Conditions 1/(tCP32KHz) Crystal Oscillator Frequency CCRYSTAL32 Load Capacitance CLEXT32(2) External Load Capacitance Min Typ Max Unit – 32.768 – kHz Crystal @ 32.
SAM9G20 40.5.2 32 kHz Crystal Characteristics Table 40-11: 32 kHz Crystal Characteristics Symbol Parameter Conditions ESR Equivalent Series Resistor Rs Cm CSHUNT 40.5.3 Min Typ Max Unit Crystal @ 32.768 kHz – 50 100 kΩ Motional Capacitance Crystal @ 32.768 kHz – – 3 fF Shunt Capacitance Crystal @ 32.
SAM9G20 40.5.5 Main Oscillator Characteristics Table 40-14: Main Oscillator Characteristics Symbol Parameter 1/ (tCPMAIN) Crystal Oscillator Frequency CCRYSTAL Crystal Load Capacitance CLEXT(7) External Load Capacitance Conditions Min Typ Max Unit 3 16 20 MHz 12.5 – 17.5 pF CCRYSTAL = 12.5 pF(6) – 16 – pF (6) – 26 – pF 40 50 60 % CCRYSTAL = 17.5 pF Duty Cycle VDDOSC = 3 to 3.
SAM9G20 Figure 40-3: Main Oscillator Schematic SAM9G20 XIN XOUT GNDPLL 1K CCRYSTAL CLEXT 40.5.6 CLEXT Crystal Characteristics Table 40-15: Symbol Crystal Characteristics Parameter Conditions Min Typ Fundamental @ 3 MHz Equivalent Series Resistor Rs Unit 200 Fundamental @ 8 MHz ESR Max 100 – – Fundamental @ 16 MHz 80 Fundamental @ 20 MHz 50 Ω Cm Motional Capacitance – – 8 pF CSHUNT Shunt Capacitance – – 7 pF 40.5.
SAM9G20 Following configuration of ICPLLA and OUTA must be done for each PLLA frequency range. Table 40-17: Table 40-18: PLLA Frequency Regarding ICPLLA and OUTA PLL Frequency Range (MHz) ICPLLA 745–800 0 0 0 695–750 0 0 1 645–700 0 1 0 595–650 0 1 1 545–600 1 0 0 495–550 1 0 1 445–500 1 1 0 400–450 1 1 1 PLLB Characteristics Symbol Parameter Conditions fOUT Output Frequency Field CKGR_PLL.
SAM9G20 40.7 ADC Characteristics Table 40-20: ADC Characteristics 9-bit Mode Code Parameter R Condition & Notes Min Typ Max Unit Resolution – 9 – Bits INL Integral Non-linearity – – ±2 LSB DNL Differential Non-linearity No missing code -1 – +2 LSB EO Offset Error Not including VREFN error – – ±3 LSB EG Gain Error -1.5 – 3.
SAM9G20 Table 40-22: External Voltage Reference Input Parameter Conditions Min Typ Max Unit 2.4 – VDDANA V ADVREF Average Current – – 220 µA Current Consumption on VDDANA – 300 620 µA Min Typ Max Unit Input Voltage Range 0 – ADVREF V Input Leakage Current – – 1 µA Input Capacitance – 8 – pF ADVREF Input Voltage Range Table 40-23: Analog Inputs Parameter 40.
SAM9G20 40.9 Core Power Supply POR Characteristics Table 40-25: Power-On-Reset Characteristics Symbol Parameter Conditions Min Typ Max Unit VT+ Threshold Voltage Rising Minimum Slope of +1.0V/100ms 0.5 0.7 0.89 V VT- Threshold Voltage Falling 0.4 0.6 0.85 V tRST Reset Time 30 70 130 µs 40.10 EBI Timings SMC timings are given in Max (TA = 85°C, VDDCORE = 0.9V) corner. Timings are given assuming a capacitance load on data, control and address pads as defined in Table 40-26.
SAM9G20 Table 40-28: SMC Read Signals - NCS Controlled (READ_MODE = 0) Min Symbol Parameter 1.8V VDDIOM Supply 3.3V VDDIOM Supply Unit 12.6 11.0 ns 0 0 ns 9.2 7.6 ns 0 0 ns (ncs rd setup + ncs rd pulse) * tCPMCK - 0.8 (ncs rd setup + ncs rd pulse) * tCPMCK - 0.
SAM9G20 Table 40-30: SMC Write NCS Controlled (WRITE_MODE = 0) Min Symbol Parameter 1.8V VDDIOM Supply 3.3V VDDIOM Supply Unit SMC22 Data Out Valid before NCS High ncs wr pulse * tCPMCK - 0.8 ncs wr pulse * tCPMCK - 0.7 ns SMC23 NCS Pulse Width ncs wr pulse * tCPMCK + 0.1 ncs wr pulse * tCPMCK - 0.1 ns SMC24 NBS0/A0 NBS1, NBS2/A1, NBS3, A2–A25 valid before NCS low ncs wr setup * tCPMCK - 0.6 ncs wr setup * tCPMCK - 0.
SAM9G20 Figure 40-5: SMC Timings - NRD Controlled Read and NWE Controlled Write SMC21 SMC5 SMC17 SMC5 SMC17 SMC19 A0/A1/NBS[3:0]/A2–A25 SMC6 SMC18 SMC21 SMC6 SMC18 SMC20 NCS SMC7 SMC7 NRD SMC1 SMC2 SMC15 SMC21 SMC3 SMC15 SMC4 SMC19 D0–D31 NWE SMC16 NRD Controlled READ with NO HOLD NWE Controlled WRITE with NO HOLD SMC16 NRD Controlled READ with HOLD NWE Controlled WRITE with HOLD 40.
SAM9G20 Table 40-33: SDRAMC Characteristics Timings Standard PC100 Parameter Min Max Unit SDRAM Controller Clock Frequency – 100 MHz Control/Address/Data In Setup(1)(2) 2 – ns 1 – ns Data Out Access time after SDCK rising – 6 ns Data Out change time after SDCK rising 3 – ns SDRAM Controller Clock Frequency – 133 MHz 1.5 – ns 0.8 – ns Data Out Access time after SDCK rising – 5.4 ns Data Out change time after SDCK rising 3.
SAM9G20 40.12 Peripheral Timings 40.12.1 EMAC Timings are given assuming a capacitance load on data and clock as defined in Table 40-34. Table 40-34: Capacitance Load on Data, Clock Pads Corner I/O Supply Max 3.3V 20 pF 1.8V 20 pF The Ethernet controller satisfies the timings of standard in Max corner.
SAM9G20 Figure 40-6: EMAC MII Mode EMDC EMAC1 EMAC3 EMAC2 EMDIO EMAC4 EMAC5 EMAC6 EMAC7 ECOL ECRS ETXCK EMAC8 ETXER EMAC9 ETXEN EMAC10 ETX[3:0] ERXCK EMAC11 EMAC12 ERX[3:0] EMAC13 EMAC14 EMAC15 EMAC16 ERXER ERXDV DS60001516A-page 756 2017 Microchip Technology Inc.
SAM9G20 40.12.1.
SAM9G20 • Slave Write Mode 1 f SPCK Max = -----------------------------------------------------------------------------2x ( S PI 6max ( orSPI 9max ) + t su ) For 3.3V I/O domain and SPI6, fSPCKMax = 18.7 MHz. tsu is the setup time from the master before sampling data. 40.12.2.2 SPI Timings SPI timings are given assuming a capacitance load on MISO, SPCK and MOSI as defined in Table 40-38. Table 40-38: Capacitance Load for MISO, SPCK and MOSI Corner Figure 40-8: Supply Max 1.8V/3.
SAM9G20 Figure 40-10: SPI Slave Mode 0 and 3 SPCK SPI6 MISO SPI7 SPI8 SPI10 SPI11 MOSI Figure 40-11: SPI Slave Mode 1 and 2 SPCK SPI9 MISO MOSI Figure 40-12: SPI Slave Mode - NPCS Timings SPI15 SPI14 SPI6 SPCK (CPOL = 0) SPI12 SPI9 SPI13 SPCK (CPOL = 1) SPI16 MISO 2017 Microchip Technology Inc.
SAM9G20 Table 40-39: SPI Timings Symbol Parameter SPI0 Conditions Min Max Unit MISO Setup time before SPCK rises 14.5 + 0.5 * tCPMCK – ns SPI1 MISO Hold time after SPCK rises -11.6 - 0.5 * tCPMCK – ns SPI2 SPCK rising to MOSI -0.6 – ns SPI3 MISO Setup time before SPCK falls 14.7 + 0.5 * tCPMCK – ns SPI4 MISO Hold time after SPCK falls -11.7 - 0.5 * tCPMCK – ns SPI5 SPCK falling to MOSI -0.7 – ns SPI6 SPCK falling to MISO 14.
SAM9G20 Figure 40-13: SSC Transmitter, TK and TF in Output TK (CKI = 1) TK (CKI = 0) SSC0 TF/TD Figure 40-14: SSC Transmitter, TK in Input and TF in Output TK (CKI = 1) TK (CKI = 0) SSC1 TF/TD Figure 40-15: SSC Transmitter, TK in Output and TF in Input TK (CKI=1) TK (CKI=0) SSC2 SSC3 TF SSC0 TD 2017 Microchip Technology Inc.
SAM9G20 Figure 40-16: SSC Transmitter, TK and TF in Input SSC15 TK (CKI = 0) SSC14 SSC14 TK (CKI = 1) SSC6 SSC5 TF SSC7 TD Figure 40-17: SSC Receiver RK and RF in Input RK (CKI=0) RK (CKI=1) SSC6 SSC7 RF/RD Figure 40-18: SSC Receiver, RK in input and RF in Output RK (CKI=1) RK (CKI=0) SSC6 SSC7 RD SSC8 RF DS60001516A-page 762 2017 Microchip Technology Inc.
SAM9G20 Figure 40-19: SSC Receiver, RK and RF in Output RK (CKI=1) RK (CKI=0) SSC9 SSC10 RD SSC11 RF Figure 40-20: SSC Receiver, RK in Output and RF in Input RK (CKI=0) RK (CKI=1) SSC9 SSC10 RF/RD Table 40-41: Symbol SSC Timings 3.3V Domain Parameter Conditions Min Max Unit Transmitter SSC0 TK edge to TF/TD (TK output, TF output) -2.7 3.7 ns SSC1 TK edge to TF/TD (TK input, TF output) -2.7 3.7 ns SSC2 TF setup time before TK edge (TK output) 15.
SAM9G20 Table 40-41: SSC Timings 3.3V Domain (Continued) Symbol Parameter SSC11 Conditions Min Max Unit RF/RD setup time before RK edge (RK output) 15.9 - tCPMCK – ns SSC12 RF/RD hold time after RK edge (RK output) tCPMCK - 6.5 – ns SSC13 RK edge to RF (RK output) -2.8 – ns SSC14(1) TK rise time or fall time 10 to 90% – 10 ns SSC15(1) TK low or high time VTK>VIH or VTK
SAM9G20 40.12.4 ISI Timings Timings are given assuming a capacitance load on clock and data signals as defined in Table 40-43. Table 40-43: Capacitance Load Corner Figure 40-21: Supply Max 3.3V 30 pF 1.8V 20 pF ISI Timing Diagram PIXCLK ISI3 DATA[7:0] VSYNC HSYNC Table 40-44: Valid Data ISI1 Valid Data Valid Data ISI2 ISI Timings with Peripheral Supply 3.3V Symbol Parameter Min Max Unit ISI1 DATA/VSYNC/HSYNC setup time 4.5 – ns ISI2 DATA/VSYNC/HSYNC hold time 1.
SAM9G20 Figure 40-22: MCI Timings MCI1 CLK MCI2 MCI3 CMD_DAT Input MCI4 MCI5 CMD_DAT Output Shaded areas are not valid Table 40-46: Symbol MCI Timings CLOAD Min Max 25 pF – 25 100 pF – 20 250 pF – 20 – – 400 kHz CLK Low time 100 pF 10 – ns CLK High time 100 pF 10 – ns CLK Rise time 100 pF – 10 ns CLK Fall time 100 pF – 10 ns CLK Low time 250 pF 50 – ns CLK High time 250 pF 50 – ns CLK Rise time 250 pF – 50 ns CLK Fall time 250 pF – 50 ns MCI2 I
SAM9G20 40.12.6 UDP Timings Figure 40-23: USB Data Signal Rise and Fall Times Rise Time Fall Time 90% VCRS 10% Differential Data Lines 10% tr tf REXT = 27 ohms fOSC = 6 MHz/750 kHz Buffer Table 40-47: CLOAD In Full Speed Symbol Parameter Conditions tr Transition Rise Time tf Transition Fall Time trfm Rise/Fall time Matching 2017 Microchip Technology Inc. Min Typ Max Unit CLOAD = 50 pF 4 – 20 ns CLOAD = 50 pF 4 – 20 ns 90 – 111.
SAM9G20 41. Mechanical Characteristics 41.1 217-ball LFBGA Package Drawing Figure 41-1: Table 41-1: 217-ball LFBGA Package Drawing 217-ball LFBGA Soldering Information Ball Land 0.43 mm +/- 0.05 Soldering Mask Opening 0.30 mm +/- 0.
SAM9G20 41.1.1 Soldering Profile – 217-ball LFBGA Table 41-5 gives the recommended soldering profile from J-STD-20. Table 41-5: Soldering Profile – 217-ball LFBGA Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/sec. max. Preheat Temperature 175°C ±25°C 180 sec. max. Temperature Maintained Above 217°C 60 sec. to 150 sec. Time within 5°C of Actual Peak Temperature 20 sec. to 40 sec. Peak Temperature Range 260 +0°C Ramp-down Rate 6°C/sec. max.
SAM9G20 41.2 247-ball TFBGA Package Drawing Figure 41-2: 247-ball TFBGA Drawing Table 41-6: 247-ball TFBGA Ball Information Ball Pitch 0.50 mm ± 0.05 Ball Diameter 0.30 mm ± 0.05 Table 41-7: 247-ball TFBGA Soldering Information Ball Land 0.35 mm ± 0.05 Solder Mask Opening 0.27 mm ± 0.05 DS60001516A-page 770 2017 Microchip Technology Inc.
SAM9G20 Table 41-8: Device and 247-ball TFBGA Package Maximum Weight 177 mg Table 41-9: 247-ball TFBGA Package Characteristics Moisture Sensitivity Level Table 41-10: 3 247-ball TFBGA Package Reference JEDEC Drawing Reference none JESD97 Classification e1 41.2.1 Soldering Profile – 247-ball TFBGA Table 41-5 gives the recommended soldering profile from J-STD-20. Table 41-11: Soldering Profile – 247-ball TFBGA Profile Feature Green Package Average Ramp-up Rate (217°C to Peak) 3°C/sec.
SAM9G20 42. Marking All devices are marked with the company logo and the ordering code. Additional marking has the following format: YYWWC V XXXXXXX ARM where • • • • • “YY”: Manufactory year “WW”: Manufactory week “C”: Assembly country code (optional) “V”: Revision “XXXXXXX”: Lot number DS60001516A-page 772 2017 Microchip Technology Inc.
SAM9G20 43. Ordering Information Table 43-1: SAM9G20 Ordering Information MRL A Ordering Code MRL B Ordering Code Package Carrier Type Operating Temperature Range AT91SAM9G20-CU AT91SAM9G20B-CU LFBGA217 Tray Industrial -40°C to 85°C – AT91SAM9G20B-CFU TFBGA247 Tray Industrial -40°C to 85°C 2017 Microchip Technology Inc.
SAM9G20 44. Errata Errata is gathered in two sections: Section 44.1 “SAM9G20 Errata - Revision A Parts” Section 44.2 “SAM9G20 Errata - Revision B Parts” 44.1 44.1.1 44.1.1.1 SAM9G20 Errata - Revision A Parts Analog-to-digital Converter (ADC) ADC: Sleep Mode If Sleep mode is activated while there is no activity (no conversion is being performed), it will take effect only after a conversion occurs.
SAM9G20 44.1.3.3 ECC: Unsupported hardware ECC on 16-bit NAND Flash Hardware ECC on 16-bit NAND Flash is not supported. Problem Fix/Workaround Perform the ECC by software. 44.1.4 44.1.4.1 MCI MCI: Busy Signal of R1b responses is not taken in accoun The busy status of the card during the response (R1b) is ignored for the commands CMD7, CMD28, CMD29, CMD38, CMD42, CMD56.
SAM9G20 • The main code: //user reset interrupt setting // Configure AIC controller to handle System peripheral interrupts AT91F_AIC_ConfigureIt ( AT91C_BASE_AIC, // AIC base address AT91C_ID_SYS, // System peripheral ID AT91C_AIC_PRIOR_HIGHEST, // Max priority AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED, // Level sensitive sysc_handler ); // Enable SYSC interrupt in AIC AT91F_AIC_EnableIt(AT91C_BASE_AIC, AT91C_ID_SYS); *AT91C_RSTC_RMR = (0xA5<<24) | (0x4<<8) | AT91C_RSTC_URSTIEN; • The C SYS handler: extern void
SAM9G20 44.1.6 44.1.6.1 Serial Peripheral Interface (SPI) SPI: Bad Serial Clock Generation on second chip_select when SCBR = 1, CPOL = 1 and NCPHA = 0 If the SPI is used in the following configuration: • Master mode • CPOL = 1 and NCPHA = 0 • multiple chip selects used with one transfer with Baud rate (SCBR) equal to 1 (i.e.
SAM9G20 44.1.7.4 SSC: Periodic Transmission Limitations in Master Mode If Last Significant Bit is sent first (MSBF = 0) the first TAG during the frame synchro is not sent. Problem Fix/Workaround None. 44.1.8 44.1.8.1 Shutdown Controller (SHDWC) SHDWC: SHDN Signal may be Driven to Low Level Voltage During Device Power-on If only VDDBU is powered during boot sequence (No VDDCORE), the SHDN signal may be driven to low level voltage after a delay.
SAM9G20 5. 6. The Host controller raises the request for the first write transaction. By the time the transaction is completed, a frame boundary is crossed. After completing the first write transaction, the Host controller skips the second write transaction. Consequence: When this error occurs, the Host controller tries the same IN token again. Problem Fix/Workaround This problem can be avoided if the system guarantees that the status update can be completed within the same frame. 44.1.12.
SAM9G20 44.1.15 External Bus Interface (EBI) 44.1.15.1 EBI: After reset A25 is not functionnal After reset of the SAM9G20 device the PC10/A25 line is set into general purpose (GPIO) mode and not in peripheral mode. This result to prevent any access to upper memory address range (0xD0000000) as the A25 EBI line is not functionnal. Problem Fix/Workaround According to your system memory mapping, set into your low level initialization the PC10 line in peripheral A mode. 44.2 44.2.1 44.2.1.
SAM9G20 44.2.3.3 ECC: Unsupported hardware ECC on 16-bit NAND Flash Hardware ECC on 16-bit NAND Flash is not supported. Problem Fix/Workaround Perform the ECC by software. 44.2.4 44.2.4.1 MCI MCI: Busy Signal of R1b responses is not taken in account The busy status of the card during the response (R1b) is ignored for the commands CMD7, CMD28, CMD29, CMD38, CMD42, CMD56.
SAM9G20 Problem Fix/Workaround 1. 2. Avoid User Reset to generate a system reset. Trap the User Reset with an interrupt. In the interrupt routine, Power Down SDRAM properly and perform Peripheral and Processor Reset with software in assembler. Example with libV3.
SAM9G20 ;perform power down command STR r1, [r0] ;perform proc_reset and periph_reset (in the ARM pipeline) STR r3, [r2] END 44.2.6 44.2.6.1 Serial Peripheral Interface (SPI) SPI: Bad Serial Clock Generation on second chip_select when SCBR = 1, CPOL = 1 and NCPHA = 0 If the SPI is used in the following configuration: • master mode • CPOL = 1 and NCPHA = 0 • multiple chip selects used with one transfer with Baud rate (SCBR) equal to 1 (i.e.
SAM9G20 44.2.7.3 SSC: Transmitter Limitations in Slave Mode If TK is programmed as output and TF is programmed as input, it is impossible to emit data when start of edge (rising or falling) of synchro with a Start Delay equal to zero. Problem Fix/Workaround None. 44.2.7.4 SSC: Periodic Transmission Limitations in Master Mode If Last Significant Bit is sent first (MSBF = 0) the first TAG during the frame synchro is not sent. Problem Fix/Workaround None. 44.2.8 44.2.8.
SAM9G20 44.2.12 44.2.12.1 UHP UHP: Non-ISO IN Transfers Conditions: Consider the following sequence: 1. 2. 3. 4. 5. 6. The Host controller issues an IN token. The Device provides the IN data in a short packet. The Host controller writes the received data to the system memory. The Host controller is now supposed to carry out two Write transactions (TD status write and TD retirement write) to the system memory in order to complete the status update.
SAM9G20 44.2.13.2 USART: DCD is Active High instead of Low The DCD signal is active at High level in the USART Modem Mode . DCD should be active at Low level. Problem Fix/Workaround Add an inverter. 44.2.14 44.2.14.1 Power Management Controller (PMC) PMC: PMC bad frequency after MDIV switching If MDIV and another field (CSS or PRES) are changed at the same, the clock frequency may not be correct.
SAM9G20 45. Revision History In the tables that follow, the most recent version appears first. Issue Date Changes General - Template update: Moved from Atmel to Microchip template. - The datasheet is assigned a new document number (DS60001516) and revision letter is reset to A. --- Document number DS60001516 revision A corresponds to what would have been 6384 revision G. - ISBN number assigned. Section 40. “Electrical Characteristics” Table 40-45 ”ISI Timings with Peripheral Supply 1.
SAM9G20 Doc. Rev. 6384F Comments In document title, “Thumb Microcontrollers” changed to “Embedded MPU” Product name AT91SAM9G20 updated to SAM9G20 General editorial and formatting changes throughout Section “Description” Updated text Section “Features” In package information, “RoHS-compliant” updated to “Green-compliant” Section 1. “Block Diagram” Figure 1-1: “SAM9G20 Block Diagram”: - minor update in System Controller and backup area - signal range “SCK0–SCK2” corrected to “SCK0–SCK3” Section 2.
SAM9G20 Doc. Rev. 6384F Comments (Continued) Section 21. “SDRAM Controller (SDRAMC)” Table 21-8, “Register Mapping”: access “Read” corrected to “Read/Write” for SDRAMC_MDR Removed reset value from register description sections (reset values are provided in Table 21-8, “Register Mapping”) Section 22. “Error Correction Code Controller (ECC)” Table 22-1, “Register Mapping”: for ECC Control Register, removed reset value (register is write-only); ECC_CTRL corrected to ECC_CR Section 23.
SAM9G20 Doc. Rev. 6384F Comments (Continued) Section 40. “Electrical Characteristics” Added Section 40.6 “I/O Characteristics” Section 40.9 “Core Power Supply POR Characteristics”: transferred three sections “Power Sequence Requirements”, “Power-up Sequence” and “Power-down Sequence” to Section 4. “Power Considerations” Added Section 40.12.2.1 “Maximum SPI Frequency” Table 40-38, “Capacitance Load for MISO, SPCK and MOSI”: supply “1.8V” corrected to “1.8V/3.
SAM9G20 Doc. Rev 6384E Change Request Ref. Comments Product Overview: Section 4. “Power Considerations”, Removed the section “Power Consumption”. 6945 Section 5. “I/O Line Considerations”, Removed the section “Slow Clock Selection”. Boot Progam: Section 12.1 “Overview”, 2nd sentence of 6th paragraph updated...”formatted SDCard on SlotA”. 6243 CKGR: Section 24.5.
SAM9G20 Doc. Rev 6384D Doc. Rev 6384B Change Request Ref. Comments Section 41.6 “ADC”, former Channel Conversion TIme and ADC Clock table and former Transfer Characteritics table replaced by Table 41-18, “ADC Characteristics 9-bit Mode” and Table 41-19, “ADC Characteristics 10-bit Mode”. 6262 Section 44.2 “AT91SAM9G20 Errata - Revision “A” Parts”, added Section 44.2.2.1 “Boot ROM: ROM Code, Internal RC Usage with SAM-BA Boot through USB”. 6238 Change Request Ref.
SAM9G20 Doc. Rev 6384B Change Request Ref. Comments (Continued) 41.11.2 “SPI” Timings: The titles of the figures listed below have been updated. Figure 41-7. “SPI Master Mode with (CPOL = 0 and NCPHA = 1) or (CPOL =1 and NCPHA = 0)” 5592 Figure 41-8. “SPI Master Mode with (CPOL = NCPHA = 0) or (CPOL and NCPHA = 1)” Figure 41-9. “SPI Slave Mode with (CPOL = 0 and NCPHA = 1) or (CPOL = 1 and NCPHA = 0)” Figure 41-10.
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SAM9G20 Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Example: AT91SAM9 G20 B - CF U a) AT91SAM9G20B-CFU = Arm Arm926EJ-S general-purpose microprocessor, 247-ball, industrial temperature, BGA package.
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