Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
998
45.3.1 Data Timing
The two data timings using horizontal and vertical synchronization and EAV/SAV sequence synchronization are
shown in Figure 45-3 and Figure 45-4.
In the VSYNC/HSYNC synchronization, the valid data is captured with the active edge of the pixel clock (ISI_PCK),
after SFD lines of vertical blanking and SLD pixel clock periods delay programmed in the control register.
The
ITU-RBT.656-4 defines the functional timing for an 8-bit wide interface.
There are two timing reference signals, one at the beginning of each video data block SAV (0xFF000080) and one
at the end of each video data block EAV(0xFF00009D). Only data sent between EAV and SAV is captured.
Horizontal blanking and vertical blanking are ignored. Use of the SAV and EAV synchronization eliminates the
ISI_VSYNC and ISI_HSYNC signals from the interface, thereby reducing the pin count. In order to retrieve both
frame and line synchronization properly, at least one line of vertical blanking is mandatory.
Figure 45-3. HSYNC and VSYNC Synchronization
Figure 45-4. SAV and EAV Sequence Synchronization
45.3.2 Data Ordering
The RGB color space format is required for viewing images on a display screen preview, and the YCbCr color
space format is required for encoding.
All the sensors do not output the YCbCr or RGB components in the same order. The ISI allows the user to program
the same component order as the sensor, reducing software treatments to restore the right format.
ISI_VSYNC
ISI_HSYNC
ISI_PCK
Frame
1 line
YCbY CrYCb Y CrYCbY Cr
DATA[7..0]
ISII_PCK
Cr Y Cb Y Cr Y Y Cr Y Cb FF 00
DATA[7..0]
FF 00 00
80 Y Cb Y 00 9D
SAV EAVActive Video
Table 45-2. Data Ordering in YCbCr Mode
Mode Byte 0 Byte 1 Byte 2 Byte 3
Default Cb(i) Y(i) Cr(i) Y(i+1)
Mode1 Cr(i) Y(i) Cb(i) Y(i+1)
Mode2 Y(i) Cb(i) Y(i+1) Cr(i)
Mode3 Y(i) Cr(i) Y(i+1) Cb(i)