Datasheet

997
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
45.2 Block Diagram
Figure 45-2. Image Sensor Interface Block Diagram
45.3 Functional Description
The Image Sensor Interface (ISI) supports direct connection to the ITU-R BT. 601/656 8-bit mode compliant
sensors and up to 12-bit grayscale sensors. It receives the image data stream from the image sensor on the 12-bit
data bus.
This module receives up to 12 bits for data, the horizontal and vertical synchronizations and the pixel clock. The
reduced pin count alternative for synchronization is supported for sensors that embed SAV (start of active video)
and EAV (end of active video) delimiters in the data stream.
The Image Sensor Interface interrupt line is generally connected to the Advanced Interrupt Controller and can
trigger an interrupt at the beginning of each frame and at the end of a DMA frame transfer. If the SAV/EAV
synchronization is used, an interrupt can be triggered on each delimiter event.
For 8-bit color sensors, the data stream received can be in several possible formats: YCbCr 4:2:2, RGB 8:8:8,
RGB 5:6:5 and may be processed before the storage in memory. The data stream may be sent on both preview
path and codec path if the bit CODEC_ON in the ISI_CR1 is one. To optimize the bandwidth, the codec path
should be enabled only when a capture is required.
In grayscale mode, the input data stream is stored in memory without any processing. The 12-bit data, which
represent the grayscale level for the pixel, is stored in memory one or two pixels per word, depending on the
GS_MODE bit in the ISI_CR2 register. The data is stored via the preview path without any treatment (scaling, color
conversion,…). The size of the sensor must be programmed in the fields IM_VSIZE and IM_HSIZE in the ISI_CR2
register.The programming of the preview path register (ISI_PSIZE) is not necessary. The codec datapath is not
available when grayscale image is selected.
A frame rate counter allows users to capture all frames or 1 out of every 2 to 8 frames.
Timing Signals
Interface
CCIR-656
Embedded Timing
Decoder(SAV/EAV)
Pixel Sampling
Module
Clipping + Color
Conversion
YCC to RGB
2-D Image
Scaler
Pixel
Formatter
Rx Direct
Display
FIFO
Core
Video
Arbiter
Camera
AHB
Master
Interface
APB
Interface
Camera
Interrupt
Controller
Config
Registers
Clipping + Color
Conversion
RGB to YCC
Rx Direct
Capture
FIFO
Scatter
Mode
Support
Packed
Formatter
Frame Rate
YCbCr 4:2:2
8:8:8
5:6:5
RGB
CMOS
sensor
Pixel input
up to 12 bit
Hsync/Len
Vsync/Fen
CMOS
sensor
pixel clock
input
Pixel
Clock Domain
AHB
Clock Domain
APB
Clock Domain
From
Rx buffers
Camera
Interrupt Request Line
codec_on
AHB bus APB bus