Datasheet

957
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
44.3.1.11 Draw Command Queuing
Multiple block transfer, line draw or fill commands can be issued to the TDGC by writing the commands to a 64 x
16-bit wide FIFO. All drawing specific registers can be written via writes to the FIFO by writing the address, length
and the register value to the command queue.
Length is based on the number of consecutive register writes. All accesses to the command queue FIFO are by
reading/writing to the 16-bit wide TDGC_CQR. The pointer to the command queue is automatically incremented by
the controller. FIFO command size is limited to 64 half words.
In order to optimize the small command FIFO (64 half words) use, and due to the restriction of the APB access that
has to be full word only, all 32-bit registers are split into two registers. This only affects the clipping command
where the start and end coordinates of the line to be clipped could be outside the range of 2048 pixels and may
need 32 bits to define line coordinates. Thus extra accesses to the FIFO must be made if the clip line coordinate
has to be represented in 32 bits versus 16 bits. See the specific example of clipping command that shows the
change in code as described above.
Figure 44-11. Command Queuing
DRAW QUEUE
CONTROL
SBXR
ADDRESS = 0x08
TDGC FIFO TDGC REGISTERS
LENGTH = 9
SBXR
SBYR
TEXR
TEYR
LWR
LPR
CSR
LOR
GOR
SBXR
SBYR
TEXR
TEYR
LWR
LPR
CSR
LOR
GOR
BUF END = 64
READ FIFO
WRITE TO REG
RENDER LINE
CPU WRITE