Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
948
44. Two D Graphics Controller (TDGC)
44.1 Description
The Two D Graphics Controller (TDGC) features a hardware accelerator which highly simplifies drawing tasks and
graphic management operations. The hardware accelerator makes it easy to draw lines and complex polygons
and to perform block transfers within the frame buffer.
The TDGC also features a draw command queue that automatically executes a more complex drawing function
that is composed of several register accesses.
The TDGC supports access to both external video RAM mapped to any EBI chip selects and internal RAM (frame
buffer). The external video RAM can have an 8-bit, 16-bit or 32-bit data bus.
The TDGC supports 1 bit, 2 bits, 4 bits, 8 bits, 16 bits and 24 bits per pixel. The maximum virtual memory page can
be 2048 x 2048 pixels. The data written into the video RAM by draw functions can be in little endian, big endian
and WinCE format.
The TDGC is connected to the AHB (Advanced High Performance Bus) in two ways: first, as a master for reading
and writing pixel data, and second, as a slave for register configuration.