Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
908
43.6 Interrupts
The LCD Controller generates six different IRQs. All the IRQs are synchronized with the internal LCD Core Clock.
The IRQs are:
 DMA Memory error IRQ. Generated when the DMA receives an error response from an AHB slave while it is
doing a data transfer.
 FIFO underflow IRQ. Generated when the Serializer tries to read a word from the FIFO when the FIFO is
empty.
 FIFO overwrite IRQ. Generated when the DMA Controller tries to write a word in the FIFO while the FIFO is
full.
 DMA end of frame IRQ. Generated when the DMA controller updates the Frame Base Address pointers.
This IRQ can be used to implement a double-buffer technique. For more information, see “Double-buffer
Technique” on page 909.
 End of Line IRQ. This IRQ is generated when the LINEBLANK period of each line is reached and the DMA
Controller is in inactive state.
 End of Last Line IRQ. This IRQ is generated when the LINEBLANK period of the last line of the current
frame is reached and the DMA Controller is in inactive state.
Each IRQ can be individually enabled, disabled or cleared, in the LCD_IER (Interrupt Enable Register), LCD_IDR
(Interrupt Disable Register) and LCD_ICR (Interrupt Clear Register) registers. The LCD_IMR contains the mask
value for each IRQ source and the LDC_ISR contains the status of each IRQ source. A more detailed description
of these registers can be found in “LCD Controller (LCDC) User Interface” on page 912.
43.7 Configuration Sequence
The DMA Controller starts to transfer image data when the LCDC Core is activated (Write to LCD_PWR field of
PWRCON register). Thus, the user should configure the LCDC Core and configure and enable the DMA Controller
prior to activation of the LCD Controller. In addition, the image data to be shows should be available when the
LCDC Core is activated, regardless of the value programmed in the GUARD_TIME field of the PWRCON register.
To disable the LCD Controller, the user should disable the LCDC Core and then disable the DMA Controller. The
user should not enable LIP again until the LCDC Core is in IDLE state. This is checked by reading the LCD_BUSY
bit in the PWRCON register.
The initialization sequence that the user should follow to make the LCDC work is:
 Create or copy the first image to show in the display buffer memory.
 If a palletized mode is used, create and store a palette in the internal LCD Palette memory (See “Palette” on
page 895.).
 Configure the LCD Controller Core without enabling it:
 LCDCON1 register: Program the CLKVAL and BYPASS fields: these fields control the pixel clock
divisor that is used to generate the pixel clock LCDDOTCK. The value to program depends on the
LCD Core clock and on the type and size of the LCD Module used. There is a minimum value of the
LCDDOTCK clock period that depends on the LCD Controller Configuration, this minimum value can
be found in Table 43-12 on page 899. The equations that are used to calculate the value of the pixel
clock divisor can be found at the end of Section 43.5.2.8 “Time Generator” on page 898.
 LCDCON2 register: Program its fields following their descriptions in Section 43.11 “LCD Controller
(LCDC) User Interface” on page 912 and considering the type of LCD module used and the desired
working mode. Consider that not all combinations are possible.
 LCDTIM1 and LCDTIM2 registers: Program their fields according to the datasheet of the LCD module
used and with the help of Section 43.5.2.8 “Time Generator” on page 898. Note that some fields are
not applicable to STN modules and must be programmed with 0 values. Note also that there is a
limitation on the minimum value of VHDLY, HPW, HBP that depends on the configuration of the LCDC.