Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
900
 Vertical Pulse Width (VPW): LCDVSYNC pulse width is configurable in VPW field of the LCDTIM1 register.
The pulse width is equal to (VPW+1) lines.
 Vertical Back Porch: Number of inactive lines at the beginning of the frame is configurable in VBP field of
LCDTIM1 register. The number of inactive lines is equal to VBP. This field should be programmed with 0 in
STN Mode.
 Vertical Front Porch: Number of inactive lines at the end of the frame is configurable in VFP field of
LCDTIM2 register. The number of inactive lines is equal to VFP. This field should be programmed with 0 in
STN mode.
There are two other parameters to configure in this module, the HOZVAL and the LINEVAL fields of the
LCDFRMCFG:
 HOZVAL configures the number of active LCDDOTCK cycles in each line. The number of active cycles in
each line is equal to (HOZVAL+1) cycles. The minimum value of this parameter is 1.
 LINEVAL configures the number of active lines per frame. This number is equal to (LINEVAL+1) lines. The
minimum value of this parameter is 1.
Figure 43-3, Figure 43-4 and Figure 43-5 show the timing of LCDDOTCK, LCDDEN, LCDHSYNC and LCDVSYNC
signals.
Figure 43-3. STN Panel Timing, CLKMOD 0
LCDHSYNC
LCDVSYNC
LCDDEN
LCDDOTCK
LCDD
Frame Period
VHDLY+ HBP+1HPW+1 HFP+2HOZVAL+1
LCDDOTCK
LCDD
1 PCLK
1/2 PCLK 1/2 PCLK
Line Period
LCDVSYNC
LCDHSYNC
LCDDEN