Datasheet

891
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
43.5.1.3 Channel-U
This block stores the base address and the number of words transferred for this channel (frame in single scan
mode and Upper Panel in dual scan mode) since the beginning of the frame. It also generates the end of frame
signal.
It has two pointers, the base address and the number of words to transfer. When the module receives a
new_frame signal, it reloads the number of words to transfer pointer with the size of the frame/panel. When the
module receives the new_frame signal, it also reloads the base address with the base address programmed by the
host.
The size of the frame/panel can be programmed in the FRMSIZE field of the DMAFRMCFG Register. This size is
calculated as follows:
where:
X_size = ((LINESIZE+1)*Bpp+PIXELOFF)/32
Y_size = (LINEVAL+1)
 LINESIZE is the horizontal size of the display in pixels, minus 1, as programmed in the LINESIZE field of the
LCDFRMCFG register of the LCD Controller.
 Bpp is the number of bits per pixel configured.
 PIXELOFF is the pixel offset for 2D addressing, as programmed in the DMA2DCFG register. Applicable only
if 2D addressing is being used.
 LINEVAL is the vertical size of the display in pixels, minus 1, as programmed in the LINEVAL field of the
LCDFRMCFG register of the LCD Controller.
Note: X_size is calculated as an up-rounding of a division by 32. (This can also be done adding 31 to the dividend before
using an integer division by 32). When using the 2D-addressing mode (see “2D Memory Addressing” on page 910), it
is important to note that the above calculation must be executed and the FRMSIZE field programmed with every
movement of the displaying window, since a change in the PIXELOFF field can change the resulting FRMSIZE value.
43.5.1.4 Channel-L
This block has the same functionality as Channel-U, but for the Lower Panel in dual scan mode only.
43.5.1.5 Control
This block receives the request signals from the LCDC core and generates the requests for the channels.
43.5.2 LCD Controller Core
43.5.2.1 Configuration Block
The configuration block is a set of programmable registers that are used to configure the LCDC core operation.
These registers are written via the AHB slave interface. Only word access is allowed.
The description of the configuration registers can be found in “LCD Controller (LCDC) User Interface” on page 912.
43.5.2.2 Datapath
The datapath block contains five submodules: FIFO, Serializer, Palette, Dithering and Shifter. The structure of the
datapath is shown in Figure 43-2.
Frame_size
X_size*Y_size
32
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