Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
850
Access to the USB host operational registers is achieved through the AHB bus slave interface. The OpenHCI host
controller initializes master DMA transfers through the ASB bus master interface as follows:
 Fetches endpoint descriptors and transfer descriptors
 Access to endpoint data from system memory
 Access to the HC communication area
 Write status and retire transfer Descriptor
Memory access errors (abort, misalignment) lead to an “Unrecoverable Error” indicated by the corresponding flag
in the host controller operational registers.
The USB root hub is integrated in the USB host. Several USB downstream ports are available. The number of
downstream ports can be determined by the software driver reading the root hub’s operational registers. Device
connection is automatically detected by the USB host port logic.
USB physical transceivers are integrated in the product and driven by the root hub’s ports.
Over current protection on ports can be activated by the USB host controller. Atmel’s standard product does not
dedicate pads to external over current protection.
41.4 Product Dependencies
41.4.1 I/O Lines
DPs and DMs are not controlled by any PIO controllers. The embedded USB physical transceivers are controlled
by the USB host controller.
41.4.2 Power Management
The USB host controller requires a 48 MHz clock. This clock must be generated by a PLL with a correct accuracy
of ± 0.25%.
Thus the USB device peripheral receives two clocks from the Power Management Controller (PMC): the master
clock MCK used to drive the peripheral user interface (MCK domain) and the UHPCLK 48 MHz clock used to
interface with the bus USB signals (Recovered 12 MHz domain).
41.4.3 Interrupt
The USB host interface has an interrupt line connected to the Advanced Interrupt Controller (AIC).
Handling USB host interrupts requires programming the AIC before configuring the UHP.