Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
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The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the
ICE and that trace the activity of the Debug Communication Channel. The Debug Unit allows blockage of access
to the system through the ICE interface.
A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal
configuration.
The SAM9263 Debug Unit Chip ID value is 0x0196 07A0 on 32-bit width.
For further details on the Debug Unit, see Section 29. “Debug Unit (DBGU)” on page 398.
11.5.5 Embedded Trace Macrocell (ETM)
The SAM9263 features an Embedded Trace Macrocell (ETM), which is closely connected to the ARM926EJ-S
Processor. The Embedded Trace is a standard Medium+ level implementation and contains the following
resources:
 Four pairs of address comparators
 Two data comparators
 Eight memory map decoder inputs
 Two 16-bits counters
 One 3-stage sequencer
 Four external inputs
 One external output
 One 45-byte FIFO
The Embedded Trace Macrocell of the SAM9263 works in half-rate clock mode and thus integrates a clock divider.
This allows the maximum frequency of all the trace port signals not to exceed one half of the ARM926EJ-S clock
speed.
The Embedded Trace Macrocell input and output resources are not used in the SAM9263.
The Embedded Trace is a real-time trace module with the capability of tracing the ARM9EJ-S instruction and data.
For further details on Embedded Trace Macrocell, see the ARM documents:
 ETM9 (Rev2p2) Technical Reference Manual (DDI 0157F)
 Embedded Trace Macrocell Specification (IHI 0014J)
11.5.5.1 Trace Port
The Trace Port is made up of the following pins:
 TSYNC - the synchronization signal (Indicates the start of a branch sequence on the trace packet port.)
 TCLK - the Trace Port clock, half-rate of the ARM926EJ-S processor clock.
 TPS0 to TPS2 - indicate the processor state at each trace clock edge.
 TPK0 to TPK15 - the Trace Packet data value.
The trace packet information (address, data) is associated with the processor state indicated by TPS. Some
processor states have no additional data associated with the Trace Packet Port (i.e., failed condition code of an
instruction). The packet is 8-bits wide, and up to two packets can be output per cycle.