Datasheet

SAM9263 [DATASHEET]

Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16

11.5 Functional Description

11.5.1 Test Pin

One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied

at low level to ensure normal operating conditions. Other values associated with this pin are reserved for

manufacturing test.

11.5.2 Embedded In-circuit Emulator

The ARM9EJ-S Embedded In-Circuit Emulator-RT is supported via the ICE/JTAG port. It is connected to a host

computer via an ICE interface. Debug support is implemented using an ARM9EJ-S core embedded within the

ARM926EJ-S. The internal state of the ARM926EJ-S is examined through an ICE/JTAG port which allows

instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when

in debug state, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the

ARM9EJ-S registers. This data can be serially shifted out without affecting the rest of the system.

There are two scan chains inside the ARM9EJ-S processor which support testing, debugging, and programming of

the Embedded ICE-RT. The scan chains are controlled by the ICE/JTAG port.

Embedded ICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and

JTAG operations. A chip reset must be performed after JTAGSEL is changed.

For further details on the Embedded In-Circuit-Emulator-RT, see the ARM document ARM9EJ-S Technical

Reference Manual (DDI 0222A).

11.5.3 JTAG Signal Description

TMS is the Test Mode Select input which controls the transitions of the test interface state machine.

TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction

TDO is the Test Data Output line which is used to serially output the data from the JTAG registers to the equipment

controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and

propagates them to the next chip in the serial test circuit.

NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in ARM cores and used to

reset the debug logic. On Atmel ARM926EJ-S-based cores, NTRST is a Power-On Reset output. It is asserted on

power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2.5 MCK

periods.

TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment controlling the test

and not by the tested device. It can be pulsed at any frequency. Note the maximum JTAG clock rate on

ARM926EJ-S cores is 1/6th the clock of the CPU. This gives 5.45 kHz maximum initial JTAG clock rate for an

ARM9E running from the 32.768 kHz slow clock.

RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better clock handling by

emulators. From some ICE Interface probes, this return signal can be used to synchronize the TCK clock and take

not care about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only

available in JTAG ICE Mode and not in boundary scan mode.

11.5.4 Debug Unit

The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace

purposes and offers an ideal means for in-situ programming solutions and debug monitor communication.

Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with

processor time reduced to a minimum.