Datasheet

SAM9263 [DATASHEET]

Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16

696

37.6 Pulse Width Modulation Controller (PWM) User Interface

Note: 1. Some registers are indexed with “ch_num” index ranging from 0 to 3.

Table 37-2. Register Mapping

Offset

(1)

0x00 PWM Mode Register PWM_MR Read/Write 0

0x04 PWM Enable Register PWM_ENA Write-only –

0x08 PWM Disable Register PWM_DIS Write-only –

0x0C PWM Status Register PWM_SR Read-only 0

0x10 PWM Interrupt Enable Register PWM_IER Write-only –

0x14 PWM Interrupt Disable Register PWM_IDR Write-only –

0x18 PWM Interrupt Mask Register PWM_IMR Read-only 0

0x1C PWM Interrupt Status Register PWM_ISR Read-only 0

0x4C–0xFC Reserved – – –

0x100–0x1FC Reserved – – –

0x200 + ch_num * 0x20 + 0x00 PWM Channel Mode Register PWM_CMR Read/Write 0x0

0x200 + ch_num * 0x20 + 0x04 PWM Channel Duty Cycle Register PWM_CDTY Read/Write 0x0

0x200 + ch_num * 0x20 + 0x08 PWM Channel Period Register PWM_CPRD Read/Write 0x0

0x200 + ch_num * 0x20 + 0x0C PWM Channel Counter Register PWM_CCNT Read-only 0x0

0x200 + ch_num * 0x20 + 0x10 PWM Channel Update Register PWM_CUPD Write-only –