Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
690
37.5.2 PWM Channel
37.5.2.1 Block Diagram
Figure 37-3. Functional View of the Channel Block Diagram
Each of the four channels is composed of three blocks:
 A clock selector which selects one of the clocks provided by the clock generator described in Section 37.5.1
“PWM Clock Generator” on page 689.
 An internal counter clocked by the output of the clock selector. This internal counter is incremented or
decremented according to the channel configuration and comparators events. The size of the internal
counter is 16 bits.
 A comparator used to generate events according to the internal counter value. It also computes the PWMx
output waveform according to the configuration.
37.5.2.2 Waveform Properties
The different properties of output waveforms are:
 the internal clock selection. The internal channel counter is clocked by one of the clocks provided by the
clock generator described in the previous section. This channel parameter is defined in the CPRE field of the
PWM_CMRx. This field is reset at 0.
 the waveform period. This channel parameter is defined in the CPRD field of the PWM_CPRDx register.
- If the waveform is left aligned, then the output waveform period depends on the counter source clock and
can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024), the resulting period formula will be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
or
If the waveform is center aligned then the output waveform period depends on the counter source clock and
can be calculated:
By using the Master Clock (MCK) divided by an X given prescaler value
(with X being 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
or
Comparator PWMx output waveform
Internal
Counter
Clock
Selector
inputs
from clock
generator
inputs from
APB bus
Channel
XCPRD×()
MCK
-------------------------------
CRPD DIVA×()
MCK
------------------------------------------
CRPD DIVAB×()
MCK
----------------------------------------------
2 XCPRD××()
MCK
----------------------------------------
2 CPRD DIVA××()
MCK
---------------------------------------------------
2 CPRD× DIVB×()
MCK
---------------------------------------------------