Datasheet

687
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
37. Pulse Width Modulation Controller (PWM)
37.1 Overview
The PWM macrocell controls several channels independently. Each channel controls one square output
waveform. Characteristics of the output waveform such as period, duty-cycle and polarity are configurable through
the user interface. Each channel selects and uses one of the clocks provided by the clock generator. The clock
generator provides several clocks resulting from the division of the PWM macrocell master clock.
All PWM macrocell accesses are made through APB mapped registers.
Channels can be synchronized, to generate non overlapped waveforms. All channels integrate a double buffering
system in order to prevent an unexpected output waveform while modifying the period or the duty-cycle.
37.2 Block Diagram
Figure 37-1. Pulse Width Modulation Controller Block Diagram
PWM
Controller
APB
PWMx
PWMx
PWMx
Channel
Update
Duty Cycle
Counter
PWM0
Channel
PIO
AICPMC
MCK
Clock Generator APB Interface Interrupt Generator
Clock
Selector
Period
Comparator
Update
Duty Cycle
Counter
Clock
Selector
Period
Comparator
PWM0
PWM0