Datasheet

611
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
35.7 AC97 Controller (AC97C) User Interface
Table 35-4. Register Mapping
Offset Register Name Access Reset
0x0–0x4 Reserved – – –
0x8 Mode Register AC97C_MR Read/Write 0x0
0xC Reserved – – –
0x10 Input Channel Assignment Register AC97C_ICA Read/Write 0x0
0x14 Output Channel Assignment Register AC97C_OCA Read/Write 0x0
0x18–0x1C Reserved – – –
0x20 Channel A Receive Holding Register AC97C_CARHR Read-only 0x0
0x24 Channel A Transmit Holding Register AC97C_CATHR Write-only –
0x28 Channel A Status Register AC97C_CASR Read-only 0x0
0x2C Channel A Mode Register AC97C_CAMR Read/Write 0x0
0x30 Channel B Receive Holding Register AC97C_CBRHR Read-only 0x0
0x34 Channel B Transmit Holding Register AC97C_CBTHR Write-only –
0x38 Channel B Status Register AC97C_CBSR Read-only 0x0
0x3C Channel B Mode Register AC97C_CBMR Read/Write 0x0
0x40 Codec Channel Receive Holding Register AC97C_CORHR Read-only 0x0
0x44 Codec Channel Transmit Holding Register AC97C_COTHR Write-only –
0x48 Codec Status Register AC97C_COSR Read-only 0x0
0x4C Codec Mode Register AC97C_COMR Read/Write 0x0
0x50 Status Register AC97C_SR Read-only 0x0
0x54 Interrupt Enable Register AC97C_IER Write-only –
0x58 Interrupt Disable Register AC97C_IDR Write-only –
0x5C Interrupt Mask Register AC97C_IMR Read-only 0x0
0x60–0xFB Reserved – – –
0x100–0x124
Reserved for Peripheral DMA Controller (PDC)
registers related to channel transfers
– – –