Datasheet

507
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
32.9.5 TWI Status Register
Name: TWI_SR
Access: Read-only
• TXCOMP: Transmission Completed
0: During the length of the current frame.
1: When both holding and shift registers are empty and STOP condition has been sent, or when MSEN is set (enable TWI).
• RXRDY: Receive Holding Register Ready
0: No character has been received since the last TWI_RHR read operation.
1: A byte has been received in the TWI_RHR since the last read.
• TXRDY: Transmit Holding Register Ready
0: The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR.
1: As soon as data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the
same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI).
• OVRE: Overrun Error (clear on read)
0: TWI_RHR has not been loaded while RXRDY was set.
1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set.
• UNRE: Underrun Error
0: No underrun error.
1: No valid data in TWI_THR (TXRDY set) while trying to load the data shifter. This action automatically generated a
STOP bit in Master Mode. Reset by read in TWI_SR when TXCOMP is set.
• NACK: Not Acknowledged
0: Each data byte has been correctly received by the far-end side TWI slave component.
1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. Reset after read.
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76543210
UNRE OVRE – – – TXRDY RXRDY TXCOMP