Datasheet

491
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
32.8 Functional Description
32.8.1 Transfer format
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an
acknowledgement. The number of bytes per transfer is unlimited (see Figure 32-4).
Each transfer begins with a START condition and terminates with a STOP condition (see Figure 32-3).
 A high-to-low transition on the TWD line while TWCK is high defines the START condition.
 A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 32-3. START and STOP Conditions
Figure 32-4. Transfer Format
32.8.2 Modes of Operation
The TWI has two modes of operation:
 Master transmitter mode
 Master receiver mode
The TWI Control Register (TWI_CR) allows configuration of the interface in Master Mode. In this mode, it
generates the clock according to the value programmed in the Clock Waveform Generator Register (TWI_CWGR).
This register defines the TWCK signal completely, enabling the interface to be adapted to a wide range of clocks.
TWD
TWCK
Start Stop
TWD
TWCK
Start Address R/W Ack Data Ack Data Ack Stop