Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
488
32. Two-wire Interface (TWI)
32.1 Description
The Two-wire Interface (TWI) interconnects components on a unique two-wire bus, made up of one clock line and
one data line with speeds of up to 400 kbits per second, based on a byte-oriented transfer format. It can be used
with any Atmel Two-wire Interface bus Serial EEPROM and I²C compatible device such as Real-time Clock (RTC),
Dot Matrix/Graphic LCD Controllers and Temperature Sensor, to name but a few. The TWI is programmable as
master transmitter or master receiver with sequential or single-byte access. A configurable baud rate generator
permits the output data rate to be adapted to a wide range of core clock frequencies. Table 32-1 below lists the
compatibility level of the Atmel Two-wire Interface and a full I2C compatible device.
Notes: 1. START + b000000001 + Ack + Sr.
2. A repeated start condition is only supported in Master Receiver mode. See Section 32.8.5 “Internal Address” on
page 494.
32.2 Embedded Characteristics
 Compatible with the Atmel Implementation of the AMBA APB Bridge
 Compatible with Atmel Two-wire Interface Serial Memory and I²C Compatible Devices
(1)
 One, Two or Three Bytes Internal Address Registers for easy Serial Memory access
 7-bit or 10-bit Slave Addressing
 Sequential Read/Write Operations
Note: 1. See Table 32-1 above for details on compatibility with I²C Standard.
Table 32-1. Atmel TWI Compatibility with i2C Standard
I2C Standard Atmel TWI
Standard Mode Speed (100 kHz) Supported
Fast Mode Speed (400 kHz) Supported
7 or 10 bits Slave Addressing Supported
START BYTE
(1)
Not Supported
Repeated Start (Sr) Condition Not Fully Supported
(2)
ACK and NACK Management Supported
Slope control and input filtering (Fast mode) Not Supported
Clock stretching Supported
Multi Master Capability Not Supported