Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
358
27.9.10 PMC Clock Generator PLL B Register
Name: CKGR_PLLBR
Address: 0xFFFFFC2C
Access: Read/Write
Possible limitations on PLLB input frequencies and multiplier factors should be checked before using the PMC.
•DIVB Divider B
• PLLBCOUNT: PLL B Counter
Specifies the number of slow clock cycles before the LOCKB bit is set in PMC_SR after CKGR_PLLBR is written.
• OUTB: PLL B Clock Frequency Range
To optimize clock performance, this field must be programmed as specified in Section 46.6.5 “PLL Characteristics”.
• MULB: PLL B Multiplier
0: The PLL B is deactivated.
1 up to 2047 = The PLL B Clock frequency is the PLL B input frequency multiplied by MULB + 1.
• USBDIV: Divider for USB Clock
31 30 29 28 27 26 25 24
– – USBDIV – MULB
23 22 21 20 19 18 17 16
MULB
15 14 13 12 11 10 9 8
OUTB PLLBCOUNT
76543210
DIVB
DIVB Divider Selected
0 Divider output is 0
1 Divider is bypassed
2–255 Divider output is the selected clock divided by DIVB.
USBDIV Divider for USB Clock(s)
0 0 Divider output is PLLB clock output.
0 1 Divider output is PLLB clock output divided by 2.
1 0 Divider output is PLLB clock output divided by 4.
1 1 Reserved.