Datasheet

343
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
Once the PMC_PCKx register has been programmed, The corresponding Programmable clock must be
enabled and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR. This can be done
either by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to
PCKRDYx has been enabled in the PMC_IER. All parameters in PMC_PCKx can be programmed in a single
write operation.
If the CSS and PRES parameters are to be modified, the corresponding Programmable clock must be
disabled first. The parameters can then be modified. Once this has been done, the user must re-enable the
Programmable clock and wait for the PCKRDYx bit to be set.
Code Example:
write_register(PMC_PCK0,0x00000015)
Programmable clock 0 is main clock divided by 32.
7. Enabling Peripheral Clocks
Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled
via registers PMC_PCER and PMC_PCDR.
Depending on the system used, 23 peripheral clocks can be enabled or disabled. The PMC_PCSR provides
a clear view as to which peripheral clock is enabled.
Note: Each enabled peripheral clock corresponds to Master Clock.
Code Examples:
write_register(PMC_PCER,0x00000110)
Peripheral clocks 4 and 8 are enabled.
write_register(PMC_PCDR,0x00000010)
Peripheral clock 4 is disabled.