Datasheet

337
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
The PLL allows multiplication of the divider’s outputs. The PLL clock signal has a frequency that depends on the
respective source signal frequency and on the parameters DIV and MUL. The factor applied to the source signal
frequency is (MUL + 1)/DIV. When MUL is written to 0, the corresponding PLL is disabled and its power
consumption is saved. Re-enabling the PLL can be performed by writing a value higher than 0 in the MUL field.
Whenever the PLL is re-enabled or one of its parameters is changed, the LOCK bit (LOCKA or LOCKB) in
PMC_SR is automatically cleared. The values written in the PLLCOUNT field (PLLACOUNT or PLLBCOUNT) in
CKGR_PLLR (CKGR_PLLAR or CKGR_PLLBR), are loaded in the PLL counter. The PLL counter then
decrements at the speed of the Slow Clock until it reaches 0. At this time, the LOCK bit is set in PMC_SR and can
trigger an interrupt to the processor. The user has to load the number of Slow Clock cycles required to cover the
PLL transient time into the PLLCOUNT field. The transient time depends on the PLL filter. The initial state of the
PLL and its target frequency can be calculated using a specific tool provided by Atmel.
During the PLLA or PLLB initialization, the PMC_PLLICPR must be programmed correctly.