Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
336
Figure 26-5. Divider and PLL Block Diagram
26.4.1 PLL Filter
The PLL requires connection to an external second-order filter through the PLLRCA and/or PLLRCB pin. Figure
26-6 shows a schematic of these filters.
Figure 26-6. PLL Capacitors and Resistors
Values of R, C1 and C2 to be connected to the PLLRC pin must be calculated as a function of the PLL input
frequency, the PLL output frequency and the phase margin. A trade-off has to be found between output signal
overshoot and startup time.
26.4.2 Divider and Phase Lock Loop Programming
The divider can be set between 1 and 255 in steps of 1. When a divider field (DIV) is set to 0, the output of the
corresponding divider and the PLL output is a continuous signal at level 0. On reset, each DIV field is set to 0, thus
the corresponding PLL input clock is set to 0.
Divider B
PLLRCB
DIVB
PLL B
MULB
PLLRCA
DIVA
PLL A
Counter
PLLBCOUNT
LOCKB
PLL A
Counter
PLLACOUNT
LOCKA
MULA
OUTB
OUTA
SLCK
PLLACK
PLLBCK
Divider A
PLL B
MAINCK
GND
C1
C2
PLL
PLLRC
R