Datasheet

335
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
stops counting. Its value can be read in the MAINF field of CKGR_MCFR and gives the number of Main Clock
cycles during 16 periods of Slow Clock, so that the frequency of the crystal connected on the Main Oscillator can
be determined.
26.3.5 Main Oscillator Bypass
The user can input a clock on the device instead of connecting a crystal. In this case, the user has to provide the
external clock signal on the XIN pin. The input characteristics of the XIN pin under these conditions are given in the
product electrical characteristics section. The programmer has to be sure to set the OSCBYPASS bit to 1 and the
MOSCEN bit to 0 in the Main OSC register (CKGR_MOR) for the external clock to operate properly.
26.4 Divider and PLL Block
The PLL embeds an input divider to increase the accuracy of the resulting clock signals. However, the user must
respect the PLL minimum input frequency when programming the divider.
Figure 26-4 shows the block diagram of the divider and PLL block.
Figure 26-4. Divider and PLL Block Diagram
Divider
PLLRC
DIV
PLL
MUL
PLLCOUNT
LOCK
OUT
SLCK
MAINCK
PLLCK
PLL
Counter