Datasheet

33
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
8.9 General-purpose Backup Registers
 Twenty 32-bit general-purpose backup registers
8.10 Backup Power Switch
 Automatic switch of VDDBU to VDDCORE guaranteeing very low power consumption on VDDBU while
VDDCORE is present
8.11 Advanced Interrupt Controller
 Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor
 Thirty-two individually maskable and vectored interrupt sources
 Source 0 is reserved for the Fast Interrupt Input (FIQ)
 Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
 Programmable Edge-triggered or Level-sensitive Internal Sources
 Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
 Four External Sources plus the Fast Interrupt signal
 8-level Priority Controller
 Drives the Normal Interrupt of the processor
 Handles priority of the interrupt sources 1 to 31
 Higher priority interrupts can be served during service of lower priority interrupt
 Vectoring
 Optimizes Interrupt Service Routine Branch and Execution
 One 32-bit Vector Register per interrupt source
 Interrupt Vector Register reads the corresponding current Interrupt Vector
 Protect Mode
 Easy debugging by preventing automatic operations when protect models are enabled
 Fast Forcing
 Permits redirecting any normal interrupt source on the Fast Interrupt of the processor
8.12 Debug Unit
See DBGU Section 29.2 “Embedded Characteristics”.
8.13 Chip Identification
 Chip ID: 0x019607A0
 JTAG ID: 0x05B0C03F
 ARM926 TAP ID: 0x0792603F
8.14 PIO Controllers
 Five PIO Controllers, PIOA to PIOE, controlling a total of 160 I/O Lines
 Each PIO Controller controls up to 32 programmable I/O Lines
 PIOA has 32 I/O Lines
 PIOB has 32 I/O Lines
 PIOC has 32 I/O Lines
 PIOD has 32 I/O Lines
 PIOE has 32 I/O Lines