Datasheet

317
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
24.4.23 DMAC Channel Enable Register
Name: DMAC_ChEnReg
Address: 0x008003A0
Access: Read/Write
•CH_ENx:
0: Disable the Channel
1: Enable the Channel
Enables/Disables the channel. Setting this bit enables a channel, clearing this bit disables the channel.
The DMAC_ChEnReg.CH_EN bit is automatically cleared by hardware to disable the channel after the last AMBA transfer
of the DMA transfer to the destination has completed.Software can therefore poll this bit to determine when a DMA transfer
has completed.
• CH_EN_WEx:
The channel enable bit, CH_EN, is only written if the corresponding channel write enable bit, CH_EN_WE, is asserted on
the same AMBA write transfer.
For example, writing 0x101 writes a 1 into DMAC_ChEnReg[0], while DMAC_ChEnReg[7:1] remains unchanged.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––CH_EN_WE1CH_EN_WE0
76543210
––––––CH_EN1CH_EN0