Datasheet

31
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
8.2 Reset Controller
 Based on two Power-on-Reset cells
 One on VDDBU and one on VDDCORE
 Status of the last reset
 Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or
watchdog reset
 Controls the internal resets and the NRST pin output
 Allows shaping a reset signal for the external devices
8.3 Shutdown Controller
See SHDWC Section 17.2 “Embedded Characteristics”.
8.4 Clock Generator
 Embeds the low-power 32.768 kHz Slow Clock Oscillator
 Provides the permanent Slow Clock SLCK to the system
 Embeds the Main Oscillator
 Oscillator bypass feature
 Supports 3 to 20 MHz crystals
 Embeds 2 PLLs
 Output 80 to 240 MHz clocks
 Integrates an input divider to increase output accuracy
 1 MHz Minimum input frequency
Figure 8-2. Clock Generator Block Diagram
Power
Management
Controller
XIN
XOUT
PLLRCA
Slow Clock
SLCK
Main Clock
MAINCK
PLLA Clock
PLLACK
ControlStatus
PLL and
Divider B
PLLRCB
PLLB Clock
PLLBCK
XIN32
XOUT32
Slow Clock
Oscillator
Main
Oscillator
PLL and
Divider A
Clock Generator