Datasheet

307
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
24.4.13 Interrupt Mask Registers
Names: DMAC_MaskTfr, DMAC_MaskBlock, DMAC_MaskSrcTran, DMAC_MaskDstTran, DMAC_MaskErr
Address: 0x00800310; 0x00800318; 0x00800320; 0x00800328; 0x00800330
Access: Read/Write
The contents of the Raw Status Registers are masked with the contents of the Mask Registers: DMAC_MaskTfr,
DMAC_MaskBlock, DMAC_MaskSrcTran, DMAC_MaskDstTran, DMAC_MaskErr. Each Interrupt Mask register has a bit
allocated per channel, for example, DMAC_MaskTfr[2] is the mask bit for Channel 2’s transfer complete interrupt.
A channel’s INT_MASK bit is only written if the corresponding mask write enable bit in the INT_MASK_WE field is asserted
on the same AMBA write transfer. This allows software to set a mask bit without performing a read-modified write
operation.
For example, writing hex 01x1 to the DMAC_MaskTfr register writes a 1 into DMAC_MaskTfr[0], while DMAC_MaskTfr[7:1]
remains unchanged. Writing hex 00xx leaves DMAC_MaskTfr[7:0] unchanged.
Writing a 1 to any bit in these registers unmasks the corresponding interrupt, thus allowing the DMAC to set the appropri-
ate bit in the Status Registers.
• INT_MASKx: Interrupt Mask
0: Masked
1: Unmasked
• INT_M_WEx: Interrupt Mask Write Enable
0: Write disabled
1: Write enabled
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
––––––INT_M_WE1INT_M_WE0
76543210
––––––INT_MASK1 INT_MASK0