Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
306
24.4.12 Interrupt Status Registers
Names: DMAC_StatusTfr, DMAC_StatusBlock, DMAC_StatusSrcTran, DMAC_StatusDstTran, DMAC_StatusErr
Address: 0x008002E8; 0x008002F0; 0x008002F8; 0x00800300; 0x00800308
Access: Read-only
The address offsets are:
DMAC_StatusTfr: 0x2e8
DMAC_StatusBlock: 0x2f0
DMAC_StatusSrcTran: 0x2f8
DMAC_StatusDstTran: 0x300
DMAC_StatusErr: 0x308
•STATUSx:
All interrupt events from all channels are stored in these Interrupt Status Registers after masking: DMAC_StatusTfr,
DMAC_StatusBlock, DMAC_StatusSrcTran, DMAC_StatusDstTran, DMAC_StatusErr. Each Interrupt Status register has
a bit allocated per channel, for example, DMAC_StatusTfr[2] is Channel 2’s status transfer complete interrupt.The contents
of these registers are used to generate the interrupt signals leaving the DMAC.
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
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76543210
––––––STATUS1STATUS0