Datasheet

305
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
24.4.11 Interrupt Raw Status Registers
Names: DMAC_RawTfr, DMAC_RawBlock, DMAC_RawSrcTran, DMAC_RawDstTran, DMAC_RawErr
Address: 0x008002C0; 0x008002C8; 0x008002D0; 0x008002D8; 0x008002E0
Access: Read-only
• RAWx: Raw Interrupt for Each Channel
Interrupt events are stored in these Raw Interrupt Status Registers before masking: DMAC_RawTfr, DMAC_RawBlock,
DMAC_RawSrcTran, DMAC_RawDstTran, DMAC_RawErr. Each Raw Interrupt Status register has a bit allocated per
channel, for example, DMAC_RawTfr[2] is Channel 2’s raw transfer complete interrupt. Each bit in these registers is
cleared by writing a 1 to the corresponding location in the DMAC_ClearTfr, DMAC_ClearBlock, DMAC_ClearSrcTran,
DMAC_ClearDstTran, DMAC_ClearErr registers.
31 30 29 28 27 26 25 24
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23 22 21 20 19 18 17 16
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15 14 13 12 11 10 9 8
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76543210
––––––RAW1RAW0