Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
304
24.4.10 Interrupt Registers
The following sections describe the registers pertaining to interrupts, their status, and how to clear them. For each
channel, there are five types of interrupt sources:
 IntTfr: DMA Transfer Complete Interrupt
This interrupt is generated on DMA transfer completion to the destination peripheral.
 IntBlock: Block Transfer Complete Interrupt
This interrupt is generated on DMA block transfer completion to the destination peripheral.
 IntSrcTran: Source Transaction Complete Interrupt
This interrupt is generated after completion of the last AMBA transfer of the requested single/burst
transaction from the handshaking interface on the source side.
If the source for a channel is memory, then that channel never generates a IntSrcTran interrupt and hence
the corresponding bit in this field is not set.
 IntDstTran: Destination Transaction Complete Interrupt
This interrupt is generated after completion of the last AMBA transfer of the requested single/burst
transaction from the handshaking interface on the destination side.
If the destination for a channel is memory, then that channel never generates the IntDstTran interrupt and
hence the corresponding bit in this field is not set.
 IntErr: Error Interrupt
This interrupt is generated when an ERROR response is received from an AHB slave on the HRESP bus
during a DMA transfer. In addition, the DMA transfer is cancelled and the channel is disabled.