Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
298
24.4.6 Configuration Register for Channel x Low
Name: DMAC_CFGxL
Address: 0x00800040 [0], 0x00800098 [1]
Access: Read/Write
The address offset for each channel is: 0x40+[x * 0x58]
For example, CFG0: 0x040, CFG1: 0x098, etc.
•CH_PRIOR: Channel Priority
A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the following range [0, x – 1]
A programmed value outside this range causes erroneous behavior.
• CH_SUSP: Channel Suspend
Suspends all DMA data transfers from the source until this bit is cleared. There is no guarantee that the current transaction
will complete. Can also be used in conjunction with DMAC_CFGx.FIFO_EMPTY to cleanly disable a channel without los-
ing any data.
0: Not Suspended.
1: Suspend. Suspend DMA transfer from the source.
• FIFO_EMPTY
Indicates if there is data left in the channel's FIFO. Can be used in conjunction with DMAC_CFGx.CH_SUSP to cleanly dis-
able a channel.
1: Channel's FIFO empty
0: Channel's FIFO not empty
• HS_SEL_DST: Destination Software or Hardware Handshaking Select
This register selects which of the handshaking interfaces, hardware or software, is active for destination requests on this
channel.
0: Hardware handshaking interface. Software-initiated transaction requests are ignored.
1: Software handshaking interface. Hardware Initiated transaction requests are ignored.
If the destination peripheral is memory, then this bit is ignored.
31 30 29 28 27 26 25 24
RELOAD_DS RELOAD_SR MAX_ABRST
23 22 21 20 19 18 17 16
MAX_ABRST SR_HS_POL DS_HS_POL LOCK_B LOCK_CH
15 14 13 12 11 10 9 8
LOCK_B_L LOCK_CH_L HS_SEL_SR HS_SEL_DS FIFO_EMPT CH_SUSP
76543210
CH_PRIOR –––––