Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
294
24.4.4 Control Register for Channel x Low
Name: DMAC_CTLxL
Address: 0x00800018 [0], 0x00800070 [1]
Access: Read/Write
The address offset for each channel is: 0x18+[x * 0x58]
For example, CTL0: 0x018, CTL1: 0x070, etc.
This register contains fields that control the DMA transfer. The DMAC_CTLxL register is part of the block descriptor (linked
list item) when block chaining is enabled. It can be varied on a block-by-block basis within a DMA transfer when block
chaining is enabled.
• INT_EN: Interrupt Enable Bit
If set, then all five interrupt generating sources are enabled.
• DST_TR_WIDTH: Destination Transfer Width
• SRC_TR_WIDTH: Source Transfer Width
• DINC: Destination Address Increment
Indicates whether to increment or decrement the destination address on every destination AMBA transfer. If your device is
writing data to a destination peripheral FIFO with a fixed address, then set this field to “No change”.
00: Increment
01: Decrement
1x: No change
•SINC: Source Address Increment
Indicates whether to increment or decrement the source address on every source AMBA transfer. If your device is fetching
data from a source peripheral FIFO with a fixed address, then set this field to “No change”.
00: Increment
01: Decrement
1x: No change
31 30 29 28 27 26 25 24
– – – LLP_S_EN LLP_D_EN SMS DMS
23 22 21 20 19 18 17 16
DMS TT_FC - D_SCAT_EN S_GATH_EN SRC_MSIZE
15 14 13 12 11 10 9 8
SRC_MSIZE DEST_MSIZE SINC DINC
76543210
DINC SRC_TR_WIDTH DST_TR_WIDTH INT_EN
SRC_TR_WIDTH/DST_TR_WIDTH Size (bits)
000 8
001 16
010 32
Other Reserved