Datasheet

293
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
24.4.3 Linked List Pointer Register for Channel x
Name: DMAC_LLPx
Address: 0x00800010 [0], 0x00800068 [1]
Access: Read/Write
The address offset for each channel is: 0x10+[x * 0x58]
For example, LLP0: 0x010, LLP1: 0x068, etc.
• LOC: Address of the next LLI
Starting address in memory of next LLI if block chaining is enabled. Note that the two LSBs of the starting address are not
stored because the address is assumed to be aligned to a 32-bit boundary.
The user need to program this register to point to the first Linked List Item (LLI) in memory prior to enabling the channel if
block chaining is enabled.
The LLP register has two functions:
1. The logical result of the equation LLP.LOC != 0 is used to set up the type of DMA transfer (single or multi-
block).
If LLP.LOC is set to 0x0, then transfers using linked lists are NOT enabled. This register must be programmed prior to
enabling the channel in order to set up the transfer type.
It (LLP.LOC != 0) contains the pointer to the next Linked Listed Item for block chaining using linked lists.
2. The DMAC_LLPx register is also used to point to the address where write back of the control and
source/destination status information occurs after block completion.
31 30 29 28 27 26 25 24
LOC
23 22 21 20 19 18 17 16
LOC
15 14 13 12 11 10 9 8
LOC
76543210
LOC 0 0