Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
288
24.4 DMA Controller (DMAC) User Interface
Table 24-3. Register Mapping
Offset Register Name Access Reset
0x0 Channel 0 Source Address Register DMAC_SAR0 Read/Write 0x0
0x4 Reserved – – –
0x8 Channel 0 Destination Address Register DMAC_DAR0 Read/Write 0x0
0xC Reserved – – –
0x10 Channel 0 Linked List Pointer Register DMAC_LLP0 Read/Write 0x0
0x14 Reserved – – –
0x18 Channel 0 Control Register Low DMAC_CTL0L Read/Write 0x0
0x1C Channel 0 Control Register High DMAC_CTL0H Read/Write 0x0
0x20–0x3C Reserved – – –
0x40 Channel 0 Configuration Register Low DMAC_CFG0L Read/Write 0x00000c00
0x44 Channel 0 Configuration Register High DMAC_CFG0H Read/Write 0x00000004
0x48 Channel 0 Source Gather Register DMAC_SGR0 Read/Write 0x0
0x4C Reserved – – –
0x50 Channel 0 Destination Scatter Register DMAC_DSR0 Read/Write 0x0
0x54 Reserved – – –
0x58 Channel 1 Source Address Register DMAC_SAR1 Read/Write 0x0
0x5C Reserved – – –
0x60 Channel 1 Destination Address Register DMAC_DAR1 Read/Write 0x0
0x64 Reserved – – –
0x68 Channel 1 Linked List Pointer Register DMAC_LLP1 Read/Write 0x0
0x7C Reserved – – –
0x70 Channel 1 Control Register Low DMAC_CTL1L Read/Write 0x0
0x74 Channel 1 Control Register High DMAC_CTL1H Read/Write 0x0
0x78–0x94 Reserved – – –
0x98 Channel 1 Configuration Register Low DMAC_CFG1L Read/Write 0x00000c20
0x9C Channel 1 Configuration Register High DMAC_CFG1H Read/Write 0x00000004
0xa0 Channel 1 Source Gather Register DMAC_SGR1 Read/Write 0x0
0xa4 Reserved – – –
0xa8 Channel 1 Destination Scatter Register DMAC_DSR1 Read/Write 0x0
0xac–0x2bc Reserved – – –
0x2c0 Raw Status for IntTfr Interrupt DMAC_RawTfr Read-only 0x0
0x2c4 Reserved – – –
0x2c8 Raw Status for IntBlock Interrupt DMAC_RawBlock Read-only 0x0
0x2cc Reserved – – –
0x2d0 Raw Status for IntSrcTran Interrupt DMAC_RawSrcTran Read-only 0x0