Datasheet

287
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
24.3.6 Disabling a Channel Prior to Transfer Completion
Under normal operation, software enables a channel by writing a ‘1’ to the Channel Enable Register,
DMAC_ChEnReg.CH_EN, and hardware disables a channel on transfer completion by clearing the
DMAC_ChEnReg.CH_EN register bit.
The recommended way for software to disable a channel without losing data is to use the CH_SUSP bit in
conjunction with the FIFO_EMPTY bit in the Channel Configuration Register (DMAC_CFGx) register.
1. If software wishes to disable a channel prior to the DMA transfer completion, then it can set the
DMAC_CFGx.CH_SUSP bit to tell the DMAC to halt all transfers from the source peripheral. Therefore, the
channel FIFO receives no new data.
2. Software can now poll the DMAC_CFGx.FIFO_EMPTY bit until it indicates that the channel FIFO is empty.
3. The DMAC_ChEnReg.CH_EN bit can then be cleared by software once the channel FIFO is empty.
When DMAC_CTLx.SRC_TR_WIDTH is less than DMAC_CTLx.DST_TR_WIDTH and the
DMAC_CFGx.CH_SUSP bit is high, the DMAC_CFGx.FIFO_EMPTY is asserted once the contents of the FIFO do
not permit a single word of DMAC_CTLx.DST_TR_WIDTH to be formed. However, there may still be data in the
channel FIFO but not enough to form a single transfer of DMAC_CTLx.DST_TR_WIDTH width. In this
configuration, once the channel is disabled, the remaining data in the channel FIFO are not transferred to the
destination peripheral. It is permitted to remove the channel from the suspension state by writing a ‘0’ to the
DMAC_CFGx.CH_SUSP register. The DMA transfer completes in the normal manner.
Note: If a channel is disabled by software, an active single or burst transaction is not guaranteed to receive an
acknowledgement.
24.3.6.1 Abnormal Transfer Termination
A DMAC DMA transfer may be terminated abruptly by software by clearing the channel enable bit,
DMAC_ChEnReg.CH_EN. This does not mean that the channel is disabled immediately after the
DMAC_ChEnReg.CH_EN bit is cleared over the AHB slave interface. Consider this as a request to disable the
channel. The DMAC_ChEnReg.CH_EN must be polled and then it must be confirmed that the channel is disabled
by reading back 0. A case where the channel is not be disabled after a channel disable request is where either the
source or destination has received a split or retry response. The DMAC must keep re-attempting the transfer to the
system HADDR that originally received the split or retry response until an OKAY response is returned. To do
otherwise is an AMBA protocol violation.
Software may terminate all channels abruptly by clearing the global enable bit in the DMAC Configuration Register
(DMAC_DmaCfgReg[0]). Again, this does not mean that all channels are disabled immediately after the
DMAC_DmaCfgReg[0] is cleared over the AHB slave interface. Consider this as a request to disable all channels.
The DMAC_ChEnReg must be polled and then it must be confirmed that all channels are disabled by reading back
‘0’.
Note: If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to the destination
peripheral and is not present when the channel is re-enabled. For read sensitive source peripherals such as a source
FIFO this data is therefore lost. When the source is not a read sensitive device (i.e., memory), disabling a channel
without waiting for the channel FIFO to empty may be acceptable as the data is available from the source peripheral
upon request and is not lost.
Note: If a channel is disabled by software, an active single or burst transaction is not guaranteed to receive an
acknowledgement.