Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
284
Note: The values in the LLI.DMAC_DARx location of each Linked List Item (LLI) in memory, although fetched during an LLI
fetch, are not used.
4. Write the channel configuration information into the DMAC_CFGx register for channel x.
1. Designate the handshaking interface type (hardware or software) for the source and destination peripher-
als. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits,
respectively. Writing a ‘0’ activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘1’ activates the software handshaking interface to handle
source/destination requests.
2. If the hardware handshaking interface is activated for the source or destination peripheral, assign hand-
shaking interface to the source and destination peripherals. This requires programming the SRC_PER and
DEST_PER bits, respectively.
5. Make sure that all LLI.DMAC_CTLx register locations of the LLI (except the last) are set as shown in Row 8
of Table 24-2 on page 268, while the LLI.DMAC_CTLx register of the last Linked List item must be set as
described in Row 1 of Table 24-2. Figure 24-8 on page 274 shows a Linked List example with two list items.
6. Make sure that the LLI.DMAC_LLPx register locations of all LLIs in memory (except the last) are non-zero
and point to the next Linked List Item.
7. Make sure that the LLI.DMAC_SARx location of all LLIs in memory point to the start source block address
proceeding that LLI fetch.
8. Make sure that the LLI.DMAC_CTLx.DONE field of the LLI.DMAC_CTLx register locations of all LLIs in
memory is cleared.
9. If gather is enabled (DMAC_CTLx.S_GATH_EN is enabled), program the DMAC_SGRx for channel x.
10. If scatter is enabled (DMAC_CTLx.D_SCAT_EN is enabled), program the DMAC_DSRx for channel x.
11. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear
registers: DMAC_ClearTfr, DMAC_ClearBlock, DMAC_ClearSrcTran, DMAC_ClearDstTran,
DMAC_ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts
have been cleared.
12. Program the DMAC_CTLx, DMAC_CFGx registers according to Row 8 as shown in Table 24-2 on page 268
13. Program the DMAC_LLPx register with DMAC_LLPx(0), the pointer to the first Linked List item.
14. Finally, enable the channel by writing a ‘1’ to the DMAC_ChEnReg.CH_EN bit. The transfer is performed.
Make sure that bit 0 of the DMAC_DmaCfgReg register is enabled.
15. The DMAC fetches the first LLI from the location pointed to by DMAC_LLPx(0).
Note: The LLI.DMAC_SARx, LLI.DMAC_DARx, LLI.DMAC_LLPx and LLI.DMAC_CTLx registers are fetched. The
LLI.DMAC_DARx location of the LLI although fetched is not used. The DMAC_DARx in the DMAC remains
unchanged.
16. Source and destination requests single and burst DMAC transactions to transfer the block of data (assuming
non-memory peripherals). The DMAC acknowledges at the completion of every transaction (burst and
single) in the block and carry out the block transfer.
17. The DMAC does not wait for the block interrupt to be cleared, but continues and fetches the next LLI from
the memory location pointed to by current DMAC_LLPx register and automatically reprograms the
DMAC_SARx, DMAC_CTLx and DMAC_LLPx channel registers. The DMAC_DARx is left unchanged. The
DMA transfer continues until the DMAC samples the DMAC_CTLx and DMAC_LLPx registers at the end of
a block transfer match that described in Row 1 of Table 24-2 on page 268. The DMAC then knows that the
previous block transferred was the last block in the DMA transfer.
The DMAC transfer might look like that shown in Figure 24-15 on page 285. Note that the destination address is
decrementing.