Datasheet

283
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
Figure 24-14. DMA Transfer for Source Address Auto-reloaded and Contiguous Destination Address
Multi-block DMA Transfer with Linked List for Source and Contiguous Destination Address (Row 8)
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the linked list in memory. Write the control information in the LLI.DMAC_CTLx register location of the
block descriptor for each LLI in memory for channel x. For example, in the register, you can program the
following:
1. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control
device by programming the TT_FC of the DMAC_CTLx register.
2. Set up the transfer characteristics, such as:
 i. Transfer width for the source in the SRC_TR_WIDTH field.
 ii. Transfer width for the destination in the DST_TR_WIDTH field.
 iii. Source master layer in the SMS field where source resides.
 iv. Destination master layer in the DMS field where destination resides.
 v. Incrementing/decrementing or fixed address for source in SINC field.
 vi. Incrementing/decrementing or fixed address for destination DINC field.
3. Write the starting destination address in the DMAC_DARx for channel x.
Channel Enabled by
software
Block Transfer
Reload SARx, CTLx
Channel Disabled by
hardware
Block Complete interrupt
generated here
DMAC Transfer Complete
interrupt generated here
yes
no
no
yes
Stall until Block Complete
interrupt cleared by software
CTLx.INT_EN=1
&&
MASKBLOCK[x]=1?
Is DMAC in Row1 of
DMAC State Machine Table?