Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
282
7. The DMA transfer proceeds as follows:
1. If interrupts are enabled (DMAC_CTLx.INT_EN = 1) and the block complete interrupt is un-masked
(DMAC_MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the block complete interrupt
when the block transfer has completed. It then stalls until the block complete interrupt is cleared by soft-
ware. If the next block is to be the last block in the DMA transfer, then the block complete ISR (interrupt
service routine) should clear the source reload bit, DMAC_CFGx.RELOAD_SR. This puts the DMAC into
Row1 as shown in Table 24-2 on page 268. If the next block is not the last block in the DMA transfer then
the source reload bit should remain enabled to keep the DMAC in Row3 as shown in Table 24-2 on page
268.
2. If interrupts are disabled (DMAC_CTLx.INT_EN = 0) or the block complete interrupt is masked
(DMAC_MaskBlock[x] = 1’b0, where x is the channel number) then hardware does not stall until it detects a
write to the block complete interrupt clear register but starts the next block transfer immediately. In this case
software must clear the source reload bit, DMAC_CFGx.RELOAD_SR, to put the device into ROW 1 of
Table 24-2 on page 268 before the last block of the DMA transfer has completed.
The transfer is similar to that shown in Figure 24-13.
The DMA Transfer flow is shown in Figure 24-14 on page 283.
Figure 24-13. Multi-block Transfer with Source Address Auto-reloaded and Contiguous Destination Address
Address of
Source Layer
Address of
Destination Layer
Source Blocks
Destination Blocks
SAR
Block0
Block1
Block2
DAR(1)
DAR(0)
DAR(2)