Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
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 Multiple device adaptability
 Compliant with LCD Module
 Control signals programmable setup, pulse and hold time for each Memory Bank
 Multiple Wait State Management
 Programmable Wait State Generation
 External Wait Request
 Programmable Data Float Time
 Slow Clock mode supported
7.2.3 SDRAM Controller
 Supported devices
 Standard and Low-power SDRAM (Mobile SDRAM)
 Numerous configurations supported
 2K, 4K, 8K Row Address Memory Parts
 SDRAM with two or four Internal Banks
 SDRAM with 16- or 32-bit Data Path
 Programming facilities
 Word, half-word, byte access
 Automatic page break when Memory Boundary has been reached
 Multibank Ping-pong Access
 Timing parameters specified by software
 Automatic refresh operation, refresh rate is programmable
 Energy-saving capabilities
 Self-refresh, power down and deep power down modes supported
 Error detection
 Refresh Error Interrupt
 SDRAM Power-up Initialization by software
 CAS Latency of 1, 2 and 3 supported
 Auto Precharge Command not used
7.2.4 Error Correction Code Controller
 Tracking the accesses to a NAND Flash device by triggering on the corresponding chip select
 Single-bit error correction and two-bit random detection
 Automatic Hamming Code Calculation while writing
 ECC value available in a register
 Automatic Hamming Code Calculation while reading
 Error Report, including error flag, correctable error flag and word address being detected erroneous
 Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-byte pages