Datasheet

279
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
the source reload bit should remain enabled to keep the DMAC in Row 7 as shown in Table 24-2 on page
268.
2. If interrupts are disabled (DMAC_CTLx.INT_EN = 0) or the block complete interrupt is masked
(DMAC_MaskBlock[x] = 1’b0, where x is the channel number) then hardware does not stall until it detects a
write to the block complete interrupt clear register but starts the next block transfer immediately. In this
case, software must clear the source reload bit, DMAC_CFGx.RELOAD_SR, to put the device into Row 1 of
Table 24-2 on page 268 before the last block of the DMA transfer has completed.
19. The DMAC fetches the next LLI from memory location pointed to by the current DMAC_LLPx register, and
automatically reprograms the DMAC_DARx, DMAC_CTLx and DMAC_LLPx channel registers. Note that
the DMAC_SARx is not re-programmed as the reloaded value is used for the next DMA block transfer. If the
next block is the last block of the DMA transfer then the DMAC_CTLx and DMAC_LLPx registers just
fetched from the LLI should match Row 1 of Table 24-2 on page 268. The DMA transfer might look like that
shown in Figure 24-11.
Figure 24-11. Multi-Block DMA Transfer with Source Address Auto-reloaded and Linked List Destination Address
The DMA Transfer flow is shown in Figure 24-12 on page 280.
Address of
Source Layer
Address of
Destination Layer
Source Blocks
Destination Blocks
SAR
Block0
Block1
Block2
BlockN
DAR(N)
DAR(1)
DAR(0)
DAR(2)