Datasheet

277
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
Figure 24-10. DMA Transfer Flow for Source and Destination Address Auto-reloaded
Multi-block Transfer with Source Address Auto-reloaded and Linked List Destination Address (Row 7)
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the chain of linked list items (otherwise known as block descriptors) in memory. Write the control
information in the LLI.DMAC_CTLx register location of the block descriptor for each LLI in memory for
channel x. For example, in the register you can program the following:
1. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control
peripheral by programming the TT_FC of the DMAC_CTLx register.
2. Set up the transfer characteristics, such as:
 i. Transfer width for the source in the SRC_TR_WIDTH field.
 ii. Transfer width for the destination in the DST_TR_WIDTH field.
 iii. Source master layer in the SMS field where source resides.
 iv. Destination master layer in the DMS field where destination resides.
 v. Incrementing/decrementing or fixed address for source in SINC field.
 vi. Incrementing/decrementing or fixed address for destination DINC field.
3. Write the starting source address in the DMAC_SARx for channel x.
Note: The values in the LLI.DMAC_SARx locations of each of the Linked List Items (LLIs) setup in memory, although fetched
during a LLI fetch, are not used.
Channel Enabled by
software
Block Transfer
Reload SARx, DARx, CTLx
Channel Disabled by
hardware
Block Complete interrupt
generated here
DMAC transfer Complete
interrupt generated here
yes
no
yes
Stall until block complete
interrupt cleared by software
CTLx.INT_EN=1
&&
MASKBLOCK[x]=1?
no
Is DMAC in Row1 of
DMAC State Machine Table?