Datasheet

SAM9263 [DATASHEET]

Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16

272

15. Source and destination request single and burst DMA transactions to transfer the block of data (assuming

non-memory peripheral). The DMAC acknowledges at the completion of every transaction (burst and single)

in the block and carry out the block transfer.

16. The DMAC does not wait for the block interrupt to be cleared, but continues fetching the next LLI from the

memory location pointed to by current DMAC_LLPx register and automatically reprograms the

DMAC_SARx, DMAC_DARx, DMAC_LLPx and DMAC_CTLx channel registers. The DMA transfer

continues until the DMAC determines that the DMAC_CTLx and DMAC_LLPx registers at the end of a block

transfer match that described in Row 1 of Table 24-2 on page 268. The DMAC then knows that the previous

block transferred was the last block in the DMA transfer. The DMA transfer might look like that shown in

Figure 24-6.

Figure 24-6. Multi-Block with Linked List Address for Source and Destination

If the user needs to execute a DMA transfer where the source and destination address are contiguous but the

amount of data to be transferred is greater than the maximum block size DMAC_CTLx.BLOCK_TS, then this can

be achieved using the type of multi-block transfer as shown in Figure 24-7 on page 273.

SAR(2)

SAR(1)

SAR(0)

DAR(2)

DAR(1)

DAR(0)

Block 2

Block 1

Block 0

Block 1

Block 2

Address of

Source Layer

Address of

Destination Layer

Source Blocks Destination Blocks