Datasheet

271
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
Multi-block Transfer with Linked List for Source and Linked List for Destination (Row 10)
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the chain of Linked List Items (otherwise known as block descriptors) in memory. Write the control
information in the LLI.DMAC_CTLx register location of the block descriptor for each LLI in memory (see
Figure 24-8 on page 274) for channel x. For example, in the register, you can program the following:
1. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow control
device by programming the TT_FC of the DMAC_CTLx register.
2. Set up the transfer characteristics, such as:
 i. Transfer width for the source in the SRC_TR_WIDTH field.
 ii. Transfer width for the destination in the DST_TR_WIDTH field.
 iii. Source master layer in the SMS field where source resides.
 iv. Destination master layer in the DMS field where destination resides.
 v. Incrementing/decrementing or fixed address for source in SINC field.
 vi. Incrementing/decrementing or fixed address for destination DINC field.
3. Write the channel configuration information into the DMAC_CFGx register for channel x.
1. Designate the handshaking interface type (hardware or software) for the source and destination peripher-
als. This is not required for memory. This step requires programming the HS_SEL_SRC/HS_SEL_DST bits,
respectively. Writing a ‘0’ activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘1’ activates the software handshaking interface to handle
source/destination requests.
2. If the hardware handshaking interface is activated for the source or destination peripheral, assign the hand-
shaking interface to the source and destination peripheral. This requires programming the SRC_PER and
DEST_PER bits, respectively.
4. Make sure that the LLI.DMAC_CTLx register locations of all LLI entries in memory (except the last) are set
as shown in Row 10 of Table 24-2 on page 268. The LLI.DMAC_CTLx register of the last Linked List Item
must be set as described in Row 1 of Table 24-2. Figure 24-7 on page 273 shows a Linked List example with
two list items.
5. Make sure that the LLI.DMAC_LLPx register locations of all LLI entries in memory (except the last) are non-
zero and point to the base address of the next Linked List Item.
6. Make sure that the LLI.DMAC_SARx/LLI.DMAC_DARx locations of all LLI entries in memory point to the
start source/destination block address preceding that LLI fetch.
7. Make sure that the LLI.DMAC_CTLx.DONE field of the LLI.DMAC_CTLx register locations of all LLI entries
in memory are cleared.
8. If gather is enabled (DMAC_CTLx.S_GATH_EN is enabled), program the DMAC_SGRx for channel x.
9. If scatter is enabled (DMAC_CTLx.D_SCAT_EN is enabled), program the DMAC_DSRx for channel x.
10. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear
registers: DMAC_ClearTfr, DMAC_ClearBlock, DMAC_ClearSrcTran, DMAC_ClearDstTran,
DMAC_ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts
have been cleared.
11. Program the DMAC_CTLx, DMAC_CFGx registers according to Row 10 as shown in Table 24-2 on page
268.
12. Program the DMAC_LLPx register with DMAC_LLPx(0), the pointer to the first Linked List item.
13. Finally, enable the channel by writing a ‘1’ to the DMAC_ChEnReg.CH_EN bit. The transfer is performed.
14. The DMAC fetches the first LLI from the location pointed to by DMAC_LLPx(0).
Note: The LLI.DMAC_SARx, LLI.DMAC_DARx, LLI.DMAC_LLPx and LLI.DMAC_CTLx registers are fetched. The DMAC
automatically reprograms the DMAC_SARx, DMAC_DARx, DMAC_LLPx and DMAC_CTLx channel registers from the
DMAC_LLPx(0).