Datasheet

27
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
7.2 External Memories
The external memories are accessed through the External Bus Interfaces 0 and 1. Each Chip Select line has a 256
Mbyte memory area assigned.
Refer to Figure 7-1 on page 24.
7.2.1 External Bus Interfaces
The SAM9263 features two External Bus Interfaces to offer more bandwidth to the system and to prevent
bottlenecks while accessing external memories.
7.2.1.1 External Bus Interface 0
 Integrates three External Memory Controllers:
 Static Memory Controller
 SDRAM Controller
 ECC Controller
 Additional logic for NAND Flash and CompactFlash
 Optional Full 32-bit External Data Bus
 Up to 26-bit Address Bus (up to 64 Mbytes linear per chip select)
 Up to 6 Chip Selects, Configurable Assignment:
 Static Memory Controller on NCS0
 SDRAM Controller or Static Memory Controller on NCS1
 Static Memory Controller on NCS2
 Static Memory Controller on NCS3, Optional NAND Flash support
 Static Memory Controller on NCS4–NCS5, Optional CompactFlash support
 Optimized for Application Memory Space
7.2.1.2 External Bus Interface 1
 Integrates three External Memory Controllers:
 Static Memory Controller
 SDRAM Controller
 ECC Controller
 Additional logic for NAND Flash
 Optional Full 32-bit External Data Bus
 Up to 23-bit Address Bus (up to 8 Mbytes linear)
 Up to 3 Chip Selects, Configurable Assignment:
 Static Memory Controller on NCS0
 SDRAM Controller or Static Memory Controller on NCS1
 Static Memory Controller on NCS2, Optional NAND Flash support
 Allows supporting an external Frame Buffer for the embedded LCD Controller without impacting processor
performance.
7.2.2 Static Memory Controller
 8-, 16- or 32-bit Data Bus
 Multiple Access Modes supported
 Byte Write or Byte Select Lines
 Asynchronous read in Page Mode supported (4- up to 32-byte page size)