Datasheet

SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
270
The “Update Method” column indicates where the values of DMAC_SARx, DMAC_DARx, DMAC_CTLx, and
DMAC_LLPx are obtained for the next block transfer when multi-block DMAC transfers are enabled.
Note: In Table 24-2 on page 268, all other combinations of DMAC_LLPx.LOC = 0, DMAC_CTLx.LLP_S_EN,
DMAC_CFGx.RELOAD_SR, DMAC_CTLx.LLP_D_EN, and DMAC_CFGx.RELOAD_DS are illegal, and causes
indeterminate or erroneous behavior.
24.3.5.1 Programming Examples
Single-block Transfer (Row 1)
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMA transfer by writing to the Interrupt Clear
registers: DMAC_ClearTfr, DMAC_ClearBlock, DMAC_ClearSrcTran, DMAC_ClearDstTran,
DMAC_ClearErr. Reading the Interrupt Raw Status and Interrupt Status registers confirms that all interrupts
have been cleared.
3. Program the following channel registers:
1. Write the starting source address in the DMAC_SARx for channel x.
2. Write the starting destination address in the DMAC_DARx for channel x.
3. Program DMAC_CTLx and DMAC_CFGx according to Row 1 as shown in Table 24-2 on page 268. Pro-
gram the DMAC_LLPx register with ‘0’.
4. Write the control information for the DMA transfer in the DMAC_CTLx register for channel x. For example, in
the register, you can program the following:
 i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow
control device by programming the TT_FC of the DMAC_CTLx register.
 ii. Set up the transfer characteristics, such as:
 Transfer width for the source in the SRC_TR_WIDTH field.
 Transfer width for the destination in the DST_TR_WIDTH field.
 Source master layer in the SMS field where source resides.
 Destination master layer in the DMS field where destination resides.
 Incrementing/decrementing or fixed address for source in SINC field.
 Incrementing/decrementing or fixed address for destination in DINC field.
5. Write the channel configuration information into the DMAC_CFGx register for channel x.
 i. Designate the handshaking interface type (hardware or software) for the source and destination
peripherals. This is not required for memory. This step requires programming the
HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’ activates the hardware handshaking
interface to handle source/destination requests. Writing a ‘1’ activates the software handshaking
interface to handle source/destination requests.
 ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign a
handshaking interface to the source and destination peripheral. This requires programming the
SRC_PER and DEST_PER bits, respectively.
6. If gather is enabled (DMAC_CTLx.S_GATH_EN is enabled), program the DMAC_SGRx for channel x.
7. If scatter is enabled (DMAC_CTLx.D_SCAT_EN, program the DMAC_DSRx for channel x.
4. After the DMAC selected channel has been programmed, enable the channel by writing a ‘1’ to the
DMAC_ChEnReg.CH_EN bit. Make sure that bit 0 of the DMAC_DmaCfgReg register is enabled.
5. Source and destination request single and burst DMA transactions to transfer the block of data (assuming
non-memory peripherals). The DMAC acknowledges at the completion of every transaction (burst and
single) in the block and carry out the block transfer.
6. Once the transfer completes, hardware sets the interrupts and disables the channel. At this time you can
either respond to the Block Complete or Transfer Complete interrupts, or poll for the Channel Enable
(DMAC_ChEnReg.CH_EN) bit until it is cleared by hardware, to detect when the transfer is complete.