Datasheet

269
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
Note: Both DMAC_SARx and DMAC_DARx updates cannot be selected to be contiguous. If this functionality is required, the
size of the Block Transfer (DMAC_CTLx.BLOCK_TS) must be increased. If this is at the maximum value, use Row 10
of Table 24-2 and set up the LLI.DMAC_SARx address of the block descriptor to be equal to the end DMAC_SARx
address of the previous block. Similarly, set up the LLI.DMAC_DARx address of the block descriptor to be equal to the
end DMAC_DARx address of the previous block.
Suspension of Transfers Between Blocks
At the end of every block transfer, an end of block interrupt is asserted if:
 interrupts are enabled, DMAC_CTLx.INT_EN = 1
 the channel block interrupt is unmasked, DMAC_MaskBlock[n] = 0, where n is the channel number.
Note: The block complete interrupt is generated at the completion of the block transfer to the destination.
For rows 6, 8, and 10 of Table 24-2 on page 268, the DMA transfer does not stall between block transfers. For
example, at the end of block N, the DMAC automatically proceeds to block N + 1.
For rows 2, 3, 4, 7, and 9 of Table 24-2 on page 268 (DMAC_SARx and/or DMAC_DARx auto-reloaded between
block transfers), the DMA transfer automatically stalls after the end of block. Interrupt is asserted if the end of block
interrupt is enabled and unmasked.
The DMAC does not proceed to the next block transfer until a write to the block interrupt clear register,
DMAC_ClearBlock[n], is performed by software. This clears the channel block complete interrupt.
For rows 2, 3, 4, 7, and 9 of Table 24-2 on page 268 (DMAC_SARx and/or DMAC_DARx auto-reloaded between
block transfers), the DMA transfer does not stall if either:
 interrupts are disabled, DMAC_CTLx.INT_EN = 0, or
 the channel block interrupt is masked, DMAC_MaskBlock[n] = 1, where n is the channel number.
Channel suspension between blocks is used to ensure that the end of block ISR (interrupt service routine) of the
next-to-last block is serviced before the start of the final block commences. This ensures that the ISR has cleared
the DMAC_CFGx.RELOAD_SR and/or DMAC_CFGx.RELOAD_DS bits before completion of the final block. The
reload bits DMAC_CFGx.RELOAD_SR and/or DMAC_CFGx.RELOAD_DS should be cleared in the ‘end of block
ISR’ for the next-to-last block transfer.
24.3.4.2 Ending Multi-block Transfers
All multi-block transfers must end as shown in Row 1 of Table 24-2 on page 268. At the end of every block
transfer, the DMAC samples the row number, and if the DMAC is in Row 1 state, then the previous block
transferred was the last block and the DMA transfer is terminated.
For rows 2,3 and 4 of Table 24-2 on page 268, (DMAC_LLPx = 0 and DMAC_CFGx.RELOAD_SR and/or
DMAC_CFGx.RELOAD_DS is set), multi-block DMA transfers continue until both the DMAC_CFGx.RELOAD_SR
and DMAC_CFGx.RELOAD_DS registers are cleared by software. They should be programmed to zero in the end
of block interrupt service routine that services the next-to-last block transfer. This puts the DMAC into Row 1 state.
For rows 6, 8, and 10 (both DMAC_CFGx.RELOAD_SR and DMAC_CFGx.RELOAD_DS cleared) the user must
set up the last block descriptor in memory such that both LLI.DMAC_CTLx.LLP_S_EN and
LLI.DMAC_CTLx.LLP_D_EN are zero.
For rows 7 and 9, the end-of-block interrupt service routine that services the next-to-last block transfer should clear
the DMAC_CFGx.RELOAD_SR and DMAC_CFGx.RELOAD_DS reload bits. The last block descriptor in memory
should be set up so that both the LLI.DMAC_CTLx.LLP_S_EN and LLI.DMAC_CTLx.LLP_D_EN are zero.
24.3.5 Programming a Channel
Three registers, the DMAC_LLPx, the DMAC_CTLx and DMAC_CFGx, need to be programmed to set up whether
single or multi-block transfers take place, and which type of multi-block transfer is used. The different transfer
types are shown in Table 24-2 on page 268.