Datasheet

267
SAM9263 [DATASHEET]
Atmel-6249N-ATARM-SAM9263-Datasheet_14-Mar-16
24.3.4 DMAC Transfer Types
A DMA transfer may consist of single or multi-block transfers. On successive blocks of a multi-block transfer, the
DMAC_SARx/DMAC_DARx in the DMAC is reprogrammed using either of the following methods:
 Block chaining using linked lists
 Auto-reloading
 Contiguous address between blocks
On successive blocks of a multi-block transfer, the DMAC_CTLx register in the DMAC is re-programmed using
either of the following methods:
 Block chaining using linked lists
 Auto-reloading
When block chaining, using linked lists is the multi-block method of choice, and on successive blocks, the
DMAC_LLPx register in the DMAC is re-programmed using the following method:
 Block chaining using linked lists
A block descriptor (LLI) consists of following registers, DMAC_SARx, DMAC_DARx, DMAC_LLPx, DMAC_CTLx.
These registers, along with the DMAC_CFGx register, are used by the DMAC to set up and describe the block
transfer.
24.3.4.1 Multi-block Transfers
Block Chaining Using Linked Lists
In this case, the DMAC re-programs the channel registers prior to the start of each block by fetching the block
descriptor for that block from system memory. This is known as an LLI update.
DMAC block chaining is supported by using a Linked List Pointer register (DMAC_LLPx) that stores the address in
memory of the next linked list item. Each LLI (block descriptor) contains the corresponding block descriptor
(DMAC_SARx, DMAC_DARx, DMAC_LLPx, DMAC_CTLx).
To set up block chaining, a sequence of linked lists must be programmed in memory.
The DMAC_SARx, DMAC_DARx, DMAC_LLPx and DMAC_CTLx registers are fetched from system memory on
an LLI update. Figure 24-5 shows how to use chained linked lists in memory to define multi-block transfers using
block chaining.
The Linked List multi-block transfers is initiated by programming DMAC_LLPx with LLPx(0) (LLI(0) base address)
and DMAC_CTLx with DMAC_CTLx.LLP_S_EN and DMAC_CTLx.LLP_D_EN.
Figure 24-5. Multi-block Transfer Using Linked Lists
System Memory
SARx
DARx
LLPx(1)
CTLx[31..0]
CTLx[63..32]
SARx
DARx
LLPx(2)
CTLx[31..0]
CTLx[63..32]
LLPx(0)
LLPx(2)
LLPx(1)
LLI(0)
LLI(1)